View EKIT01-HMC832LP6G_8961298.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fractional - n pll with integrated vco 25 mhz to 3000 mhz data sheet h mc832 features rf b andwidth: 25 mhz to 3000 mhz 3.3 v s upply maximum phase detector rate: 100 mhz ultral ow phase noise ? 110 dbc/hz in b and , typical fractional figure of merit (fom) : ? 226 dbc/hz 24 - bit step size, resolution 3 hz typical exact frequency mode with 0 hz frequency error fast frequency hopping 40 -l ead 6 mm 6 mm smt p ackage: 36 mm 2 applications cellular i nfrastructure microwave r adio wimax, wifi communications test equipment c at v e quipment dds r eplacement military tunable reference source for spuriou s- free performance functional block dia gram f igure 1. general description the hmc832 is a 3.3 v, high performance, wide band, f rac - tional -n, phase - locked loop (pll) th at features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 1500 mhz to 3000 mhz, and an integrated vco output divider (divide by 1/2/4/6 / 60/62), that enables the hmc832 to generate continuous frequencies from 25 mhz to 3000 mhz. the integrated phase detector (pd) and delta -sigma ( - ) m odulator, capable of operating at up to 100 mhz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance. industry leading phase noise and spurious performance, across all frequencies, enable the hmc832 to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. a l ow noise floor ( ? 160 dbc/hz) eliminates any contri - bution to modulator/mixer noise floor in transmitter applications. t he hmc832 is footprint - compatible to the market leading hmc830 pll with integrated vco. it features 3.3 v supply and an inn ovative programmable perfor mance technology that enables the hmc832 to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for an improved noise floor performance. additional features of the hmc832 include 12 db of rf output gain control in 1 db steps; output mute fu nction to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; p rogrammable differential or single - ended outputs, with the ability to select either output in single - ended mode; and a - modulator exact frequency mode that enables users to generate output frequencies with 0 hz frequency error. cp en en vtune rf_n rf_ p sen cp pfd r n 1, 2, 4, 6, ...62 modul at or xrefp ld/sdo sck sdi ca l vco lock detect hmc832 spi programming inter f ace contro l 12827-001 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com
hmc832* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? hmc832lp6ge evaluation board documentation application notes ? frequency hopping with hittite pllvcos application note ? pll & pllvco serial programming interface mode selection application note ? power-up & brown-out design considerations for rf pll+vco products application note ? wideband rf pll+vco and clock generation products faqs data sheet ? hmc832 data sheet tools and simulations ? adisimfrequency planner tool ? adisimpll? reference materials quality documentation ? hmc legacy pcn: lp6ce and lp6ge qfn - alternate assembly source ? package/assembly qualification test report: lp6, lp6c, lp6g (qtr: 2014-00368) ? semiconductor qualification test report: bicmos-a (qtr: 2013-00235) technical articles ? hittite introduces new 3.3v wideband pll with integrated vco ? low cost pll with integrated vco enables compact lo solutions design resources ? hmc832 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all hmc832 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
hmc832 data sheet rev. a | page 2 of 48 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? recommended operating conditions ...................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 14 ? pll subsystem overview .......................................................... 14 ? vco subsystem overview ........................................................ 14 ? spi (serial port interface) configuration of pll and vco subsystems ................................................................................... 14 ? vco subsystem .......................................................................... 16 ? pll subsystem ............................................................................ 20 ? soft reset and power-on reset ................................................ 28 ? power-down mode .................................................................... 29 ? general-purpose output (gpo) pin ....................................... 29 ? chip identification ..................................................................... 29 ? serial port .................................................................................... 29 ? applications information .............................................................. 33 ? power supply ............................................................................... 34 ? programmable performance technology................................ 34 ? loop filter and frequency changes ........................................ 34 ? rf programmable output return loss ................................... 35 ? mute mode .................................................................................. 35 ? pll register map ........................................................................... 36 ? id, read address, and rst registers ...................................... 36 ? reference divider, integer, and fractional frequency registers ....................................................................................... 36 ? vco spi register ....................................................................... 37 ? delta-sigma configuration ....................................................... 37 ? lock detect register .................................................................. 38 ? analog enable (en) register .................................................... 38 ? charge pump register ............................................................... 39 ? autocalibration register ............................................................ 39 ? phase detector (pd) register ................................................... 40 ? exact frequency mode register ............................................... 40 ? general-purpose, serial port interface, and reference divider (gpo_spi_rdiv) register ........................................ 41 ? vco tune register .................................................................... 42 ? sar register ............................................................................... 42 ? general-purpose 2 register ...................................................... 42 ? built-in self test register .......................................................... 42 ? vco subsystem register map ...................................................... 43 ? vco enable register ................................................................. 43 ? vco output divider register .................................................. 44 ? vco configuration register .................................................... 44 ? vco calibration/bias, cf calibration, and msb calibration registers ....................................................................................... 45 ? vco output power control ..................................................... 45 ? evaluation printed circuit board (pcb) ..................................... 46 ? changing evaluation board reference frequency and cp current configuration .............................................................. 46 ? evaluation kit contents ............................................................ 46 ? outline dimensions ....................................................................... 47 ? ordering guide .......................................................................... 48 ? revision history 11/14rev. 0 to rev. a this hittite microwave products data sheet has been reformatted to meet the styles and standards of analog devices, inc. updated format .................................................................. universal moved endnotes from typical performance characteristics section to the applications information section ....................... 34 changes to ordering guide .......................................................... 48
data sheet hmc832 specifications vppcp, vddls, vcc1, vcc2 = 3.3 v; rvdd, avdd, dvdd, vccpd, vcchf, vccps = 3.3 v m in imum and m ax imum s pecified across the t emp erature range of ? 40c to + 85 c. table 1 . parameter rf output characteristics output frequency 25 3000 mhz vco frequency at pll input 1500 3000 mhz rf output frequency at f vco 1500 3000 mhz output power rf output power at fundmental frequency 2000 mhz across all frequencies (see figure 25 ) maximum gain setting: vco_reg 0x07 [3:0] = 11d single - ended 7 dbm gain setting 6: vco_reg 0x07 [3:0] = 6d differential 2 dbm output power control r ange 1 db steps 12 db harmonics for fundamental mode fo mode at 2 ghz 2 nd /3 rd /4 th ?20/?29/?45 dbc fo /2 mode at 2 ghz/2 = 1 ghz 2 nd /3 rd /4 th ?26/?10/?34 dbc fo /30 mode at 3 ghz/30 = 100 mhz 2 nd /3 rd /4 th ?33/?10/?40 dbc fo /62 mode at 1550 mhz/62 = 25 mhz 2 nd /3 rd /4 th ?40/?6/?43 dbc vco output divider vco rf divider range 1, 2, 4, 6, 8, 62 1 62 pll rf divider characteristics 19- bit n - divider range (integer) maximum = 2 19 ? 1 16 524,287 3 3 33 3 3 3 v sw 40 33 3 33 3 3
hmc832 data sheet parameter power supply currents high performance mode 2500 mhz, gain 11 219 ma 800 mhz, gain 11 230 ma 2500 mhz, gain 6 226 ma 800 mhz, gain 6 237 ma 2500 mhz, gain 1 210 ma 800 mhz, gain 1 221 ma low current mode 2500 mhz, gain 6 195 ma 800 mhz, gain 6 20 5 ma 2500 mhz, gain 1 180 ma 800 mhz, gain 1 vco_reg 0x 03[1:0] = 3d 4 gain 11 (vco_reg 0x 07[3:0] = 1 1d) s ingle - ended output ( vco_reg 0x 03[3:2] = 2d ) single - ended out put gain 6 ( vco_reg 0 x07 [3:0] = 6d ) d ifferential o utput ( vco_reg 0x 03[3:2] = 3d ) differential output gain 1 (vco_reg 0x07[3:0] = 1d) differential output ( vco_reg 0x 03[3:2] = 3d ) differential o utput vco_reg 0x 03[1:0] = 1d 4 gain 6 (vco_reg 0x 07[3:0] = 6d ), differential o utput ( vco_reg 0x 03 [3:2] = 3d ) differential o utput gain 1 (vco_reg 0x 07[3:0] = 1d ), differential o utput ( vco_reg 0x 03[3:2] = 3d ) differential o utput 192 ma power - down crystal off register 0x01 = 0, crystal not clocked 10 a crystal on, 100 mhz register 0x01 = 0, crys tal clocked 100 mhz 5 ma power - on reset typical reset voltage on dvdd 700 mv minimum dvdd voltage for no reset 1. 5 v power - on reset delay 250 s vco open - loop phase noise fo @ 2 gh z 5 10 khz offset ? 88 d bc/hz 100 khz offset ? 116 d bc/hz 1 mhz offset ?139 dbc/hz 10 mhz offset ? 157 d bc/hz 100 mhz offset ? 162 d bc/hz fo @ 2 gh z /2 = 1 gh z 5 10 khz offset ? 93 d bc/hz 100 khz offset ?122 dbc/hz 1 mhz offset ? 145 d bc/hz 10 mhz offset ? 159 d bc/hz 100 mhz offset ?162 dbc/hz fo @ 3 ghz/30 = 100 mhz 5 10 khz offset ? 110 d bc/hz 100 khz offset ? 139 d bc/hz 1 mhz offs et ? 160 d bc/hz 10 mhz offset ?163 dbc/hz 100 mhz offset ? 163 d bc/hz figure of merit (fom) floor integer mode ( figure 24 ) normalized to 1 hz ? 229 d bc/hz floor fractional mode ( figure 24 ) normalized to 1 hz ?226 dbc/hz flicker (both modes) ( figure 24 ) normalized to 1 hz ? 268 d bc/hz rev. a | page 4 of 48
data sheet hmc832 parameter vco characteristics vco tuning sensitivity 2800 mhz measur ed with 1.5 v on vtune; see figure 29 2 4.6 mhz/v 2400 mhz measured with 1.5 v on vtune; see figure 29 25.8 mhz/v 2000 mhz measured with 1.5 v on vtune; see figure 29 25.2 mhz/v 1600 mhz measured with 1.5 v on vtune; see figure 29 24.3 mhz/v vco supply pushing measured with 1.5 v on vtune 2.8 mhz/v 1 measured with 100 external termination. see reference input stage section for more details. 2 slew rate of 0.5 ns/v is recommended, see reference input stage section for more details. frequency is guaranteed across process voltage and temperature from ?40c to +85c. 3 this maximum pd frequency can only be achieved if the minimum n value is respected. for example, in the case of fractional mo de, the maximum pd frequency = f vco /20 or 100 mhz, whichever is less. 4 for detailed current consumption information, refer to figure 33 and figure 36 . 5 gain setting = 6 ( vco_reg 0x07 [3:0] = 6d) in high performance mode ( vco_reg 0x03 [1:0] = 3d). timing specification s sp i write timing characteristics avdd = dvdd = 3 v, agnd = dgnd = 0 v. table 2 . spi write timing characteristics , see figure 47 parameter test conditions /comments min typ max unit t 1 sdi setup time to sclk r ising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk 32 nd rising edge to sen rising edge 10 ns t 6 recovery time 20 ns maximum serial port clock speed 50 mhz table 3 . spi read timing characteristics , see figure 48 parameter test conditions /comments min typ max unit t 1 sdi setup time to sck r ising e dge 3 ns t 2 sck rising edge to sdi hold time 3 ns t 3 sen low duratio n 10 ns t 4 sen high duration 10 ns t 5 sck rising edge to sdo time 8.2 ns + 0.2 ns/pf ns t 6 recovery time 10 ns t 7 sck 32 nd rising edge to sen rising edge 10 ns rev. a | page 5 of 48
hmc832 data sheet rev. a | page 6 of 48 absolute maximum ratings table 4. absolute maximum ratings parameter rating avdd, rvdd, dvdd, vccpd, vcchf, vccps ? ?0.3 v to +3.6 v vppcp, vddls, vcc1 ?0.3 v to +3.6 v vcc2 ?0.3 v to +3.6 v operating temperature ?40c to +85c storage temperature ?65c to +150c maximum junction temperature 150c thermal resistance ( jc ) (junction to case (ground paddle)) 9c/w reflow soldering peak temperature 260c time at peak temperature 40 sec esd sensitivity (hbm) class 1b stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. recommended operat ing conditions table 5. recommended operating conditions parameter min typ max units temperature junction temperature 1 125 c ambient temperature ?40 +85 c supply voltage avdd, rvdd, dvdd, vccpd, vcchf, vccps, vppcp, vddls, vcc1, vcc2 3.1 3.3 3.5 v 1 layout design guidelines set out in qualification test report are strongly recommended. esd caution
data sheet hmc832 pin configuration and function descripti ons f igure 2 . pin configuration t able 6 . pin function descriptions p i n no. mnemonic descriptio n 1 avdd dc power supply for analog circuitry . 2, 5, 6, 8, 9, 11 to 14, 18 to 22 , 24, 26, 34, 37, 38 nc no connect. the se pins are not connected internally; however, i t is recommended to connect these pins to rf/ dc ground externally. 3 vppcp power suppl y for charge pump analog section . 4 cp charge pump output . 7 vddls power supply for the charge pump digital section . 10 rvdd reference supply . 15 xrefp reference oscillator input . 16 dvdd dc power supply for digital (cmos) circuitry . 17 cen pll subsy stem enable . note that there is n o effect on the vco subsystem . connect to logic high for normal operation. 23 vtune vco varactor. tuning port input . 25 vcc 2 vco analog supply 2 . 27 vcc 1 vco analog supply 1 . 28 rf_n rf negative output . 29 rf_p rf posi tive output . 30 sen pll serial port enable (cmos) logic input . 31 sdi pll serial port data (cmos) logic input . 32 sck pll serial port clock (cmos) logic input . 33 ld/sdo lock detect, or serial data, or general - purpose (cmos) logic output (gpo) . 35 vcc hf dc power supply for analog circuitry . 36 vccps dc power supply for analog prescaler . 39 vccpd dc power supply for phase detector . 40 bias external bypass decoupling for precision bias circuits. note: 1.920 v 20 mv reference voltage (bias) is genera ted internally and cannot drive an external load. it m ust be measured with a 10 g meter , such as the agilent 34410a ; a normal 10 m dvm read s erroneously. ep exposed pad. the exposed pad must be connected to rf/dc ground. notes 1. nc = no connec t . do not connect t o this pin. 2. the exposed ground p ad must be connected t o rf/dc ground. 1a vdd 2 nc 3vppcp 4cp 5 nc 6 nc 7 vddls 8 nc 9 nc 10 r vdd 23 vtune 24 nc 25 vcc2 26 nc 27 vcc1 28 rf_n 29 rf_ p 30 sen 22 nc 21 nc 1 1 nc 12 nc 13 nc 15 xrefp 17cen 16 dvdd 18 nc 19 nc 20 nc 14 nc 33 ld/sdo 34 nc 35 vcchf 36 vccps 37 nc 38 nc 39 vccpd 40 bias 32 sck 31 sdi hmc832 top view (not to scale) 12827-002 rev. a | page 7 of 48
hmc832 data sheet typical performance character istics figure 3. typical closed - loop integer phase noise, 50 mhz pd frequency, output gain = 6 (vco_reg 0x07[3:0] = 6d), high performance mode (vco_reg 0x03[1:0] = 3d), phase noise integrated from 1 khz to 100 mhz, see table 12 figure 4 . open - loop vco phase noise at 1800 mhz figure 5 . free running vco phase noise at 3000 mhz figure 6. typical closed -l oop fractional phase noise, 50 mhz pd frequency, output gain = 6 (vco_reg 0x07[3:0] = 6d), high performance mode (vco_reg 0x03[1:0] = 3d), phase noise integrated from 1 khz to 100 mhz, see table 12 figure 7. closed - loop phase noise at 1800 mhz, divided by 1 to 62, pd frequency, loop filter bandwidth = 75 khz (type 2 from table 12 ), high perfor - mance mode (vco_reg 0x03[1:0] = 3d), subset of availa ble output divide ratios is shown; full range of output divide values includes 1, 2, 4, 6, 8, 58, 60, 62 figure 8. closed - loop phase noise at 3000 mhz, divided by 1 to 62, pd frequency, loop filter bandwidth = 75 khz (type 2 from table 12 ), high perfor - mance mode (vco_reg 0x03[1:0] = 3d), subset of available output divide ratios is shown; full range of output divide values includes 1, 2, 4, 6, 8, 58, 60, 62 ?170 1k 10k 100k 1m 10m 100m ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 offset (hz) phase noise (dbc/hz) 750mhz, evm = ?62.5db, or 0.075% 1600mhz, evm = ?57db or 0.141% 2500mhz, evm = ?53.3db or 0.216% 875mhz, evm = ?64.8db or 0.058% 1600mhz, evm = ?59.8db or 0.102% 2500mhz, evm = ?55.8db or 0.168% loo p bw = 127khz loo p bw = 75khz 12827-003 1k 10k 100k 1m 10m 100m offset (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) low current mode (vco_reg0x03[10] = 1d) high performance mode (vco_reg0x03[10] = 3d) 12827-004 phase noise (dbc/hz) 1k 10k 100k 1m 10m 100m offset (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?40 ?60 low current mode (vco_reg0x03[10] = 1d) high performance mode (vco_reg0x03[10] = 3d) 12827-005 ?170 1k 10k 100k 1m 10m 100m ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 offset (hz) phase noise (dbc/hz) loo p bw = 127khz 880mhz, evm = ?61.3db or 0.086% 1605mhz, evm = ?57.5db or 0.133% 2505mhz, evm = ?52db or 0.251% 880mhz, evm = ?61.8db or 0.081% 1605mhz, evm = ?57.2db or 0.138% 2505mhz, evm = ?53.9db or 0.204% loo p bw = 75khz 12827-006 1k 10k 100k 1m 10m 100m ?170 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 offset (hz) phase noise (dbc/hz) 16 32 62 1 2 8 4 12827-007 1k 10k 100k 1m 10m 100m ?170 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 offset (hz) phase noise (dbc/hz) 16 32 62 1 2 8 4 12827-008 rev. a | page 8 of 48
data sheet hmc832 figure 9 . fractional spurious performance at 904 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 (see table 12 ) figure 10 . fractional spurious performance at 2118.24 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 (see table 12 ) figure 11 . fr actional spurious performance at 2646.96 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 240 khz, loop filter type 2 (see table 12 ) figure 12 . fractional spurious performance at 1804 mhz, exact frequency mode on, 122.88 mhz x tal , pfd = 61.44 mhz, channel spacing = 200 khz, loop filter type 2 (see table 12 ) figure 13 . fractional spurious performance at 2118.24 mhz, identical configuration to figure 10 with exact frequency mode off figure 14 . fractional spurious performance at 2646.96 mhz, identical configuration to figure 11 with exact frequency mode off ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg0x03[10] = 1d) ssb integr a ted phase noise = ?64.3dbc integr a tion bandwidth = 1khz t o 100mhz snr = 61.3db, evm = 0.086%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?65.5dbc integr a tion bandwidth = 1khz t o 100mhz snr = 62.5db, evm = 0.075% phase noise integr a tion bandwidth 1khz t o 100mhz 12827-009 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?57.45dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54.45db, evm = 0.189%, phase noise integr a tion bandwidth 1khz t o 100mhz low current mode (vco_reg0x03[10] = 1d) ssb integr a ted phase noise = ?57dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54db, evm = 0.199%, phase noise integr a tion bandwidth 1khz t o 100mhz 12827-010 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg0x03[10] = 1d) ssb integr a ted phase noise = ?55.6dbc integr a tion bandwidth = 1khz t o 100mhz snr = 52.6db, evm = 0.234%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?56dbc integr a tion bandwidth = 1khz t o 100mhz snr = 53db, evm = 0.224%, phase noise integr a tion bandwidth 1khz t o 100mhz 12827-0 11 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg0x03 [10] = 1d) ssb integr a ted phase noise = ?58.7dbc integr a tion bandwidth = 1khz t o 100mhz snr = 55.7db, evm = 0.164%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?59dbc integr a tion bandwidth = 1khz t o 100mhz snr = 56db, evm = 0.158%, phase noise integr a tion bandwidth 1khz t o 100mhz 12827-012 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg0x03[10] = 1d) ssb integr a ted phase noise = ?57dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54, evm = 0.199%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?57.45dbc integr a tion bandwidth = 1khz t o 100mhz snr = 54.45db, evm = 0.189%, phase noise integr a tion bandwidth 1khz t o 100mhz 12827-013 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m low current mode (vco_reg0x03[10] = 1d) ssb integr a ted phase noise = ?55.6dbc integr a tion bandwidth = 1khz t o 100mhz snr = 52.6db, evm = 0.234%, phase noise integr a tion bandwidth 1khz t o 100mhz high performance mode (vco_reg0x03[10] = 3d) ssb integr a ted phase noise = ?56dbc integr a tion bandwidth = 1khz t o 100mhz snr = 53db, evm = 0.224%, phase noise integr a tion bandwidth 1khz t o 100mhz 12827-014 rev. a | page 9 of 48
hmc832 data sheet figure 15 . low frequency performance, 100 mhz x tal , pd frequency = 50 mhz, loop filter type 3 (see table 12 ), integer mo de, 50 mhz low - pass filter at the output of hmc832 for the 25 mhz curve only, charge pump set to maximum value figure 16 . typical spurious emissions at 2000.1 mhz, tunable reference, loop filter type 2 (see table 12 and the loop filter and frequency changes section) figure 17 . open - loop phase noise figure 18 . typical spurious emissions at 2000.1 mhz, 50 mhz fixed reference, 50 mhz pd frequency, integer boundary spur inside the loop filter bandwidth (see the loop filter and fr equency changes section) figure 19 . typical spurious vs. offset from 2 ghz, fixed 50 mhz reference vs. tunable 47.5 mhz reference (see the loop filter and frequency changes s ection) figure 20 . open - loop phase noise vs. frequency at various temperatures ?170 ?160 ?150 ?140 ?130 ?120 phase noise (dbc/hz) offset (hz) 100 1k 10k 100k 1m 10m 100m 12827-015 100mhz output 55.55mhz output 25mhz output ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m 12827-016 ?180 ?160 ?140 ?120 ?100 ?80 ?40 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m high performance mode on (vco_reg0x03[1:0] = 3d) 2854mhz 2453mhz 2013mhz 1587mhz 12827-017 ?180 ?160 ?140 ?120 ?100 ?80 ?60 phase noise (dbc/hz) offset (hz) 1k 10k 100k 1m 10m 100m 12827-018 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) output frequenc y (khz) 2000.01 2000.1 2001 typica l spurious vs. offset from 2ghz, tunable reference ~47.5mhz typica l spurious vs. offset from 2ghz, fixed reference = 50mhz 12827-019 ?170 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 1000 100 phase noise (dbc/hz) frequenc y (mhz) 300 3000 30 100khz offset al l modes 1mhz offset al l modes 100mhz offset high performance mode 100mhz offset low current mode ?40c +27c +85c 12827-020 rev. a | page 10 of 48
data sheet hmc832 figure 21 . single sideband integrated phase noise, high performance mode, loop filter type 2 (see table 12 ) figure 22 . typical single - ended output power vs. frequency (mid gain setting 6) figure 23 . typical rf output power at 2 ghz (single - ended) vs. temperature figure 24 . figure of merit figure 25 . typical output power vs. frequency and gain (single - ended) figure 26 . rf output return loss ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ssb integr a ted phase noise (dbc) output frequenc y (mhz) 0.0141 0.0447 0.1410 0.4460 100 1000 0.0045 evm (%) +85c +27c ?40c phase noise integr a ted from 10khz t o 20mhz 12827-021 ?15 ?10 ?5 0 5 10 15 output power (dbm) frequenc y (mhz) 100 25 3000 1000 phase noise integr a ted from 10khz t o 20mhz high performance mode (vco_reg0x03[1:0] = 3d) low current mode (vco_reg0x03[1:0] = 1d) return loss (vco_reg0x03[5] = 0) return loss (vco_reg0x03[5] = 1) 12827-022 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 output power (dbm) gain setting +85c +27c ?40c 12827-023 ?240 ?230 ?220 ?210 ?200 100 1k 10k 100k 1m normalized phase noise (dbc/hz) offset (hz) fom floor ty p fom vs offset fom 1/f noise 12827-024 100 25 3000 1000 ?20 ?15 ?10 ?5 0 5 10 15 20 frequenc y (mhz) output power (dbm) gain setting = 1 1 (vco_reg0x07[3:0] = 1 1d) high perfor mance mode low current mode gain setting = 5 (vco_reg0x07[3:0] = 5d) gain setting = 0 (vco_reg0x07[3:0] = 0d) 12827-025 ?30 ?25 ?20 ?15 ?10 ?5 0 output frequenc y (mhz) return loss (db) 100 25 8000 1000 return loss 0 (vco_reg0x03[5] = 0) return loss 1 (vco_reg0x03[5] = 1) 12827-026 rev. a | page 11 of 48
hmc832 data sheet figure 27 . frequency settling af ter frequency change, autocalibration enabled, loop filter bw = 127 khz (type 1, see table 12 ) figure 28 . frequency settling after frequency change, manual calibration, loop filter bw = 127 khz (type 1 in table 12 ) figure 29 . typical vco sensitivity figure 30 . phase settling after frequency change, autocalibration enabled , loop filter bw = 127 khz (type 1, see table 12 ) figure 31 . phase settling after frequency change, manual calibration figure 32 . typical tuning voltage after calibration (see the loop filter and frequency changes section) 2.2 2.4 2.6 2.8 3.0 3.2 time (s) 0 20 40 60 80 100 120 140 160 frequenc y (ghz) settling time t o < 10 degrees phase error 12827-027 time (s) 0 20 40 60 80 100 120 140 160 2.495 2.500 2.505 2.510 frequenc y (ghz) settling time t o < 10 degrees phase error n o t e : l o o p f i l t e r b a n d wi d t h = 1 2 7 k h z , l o o p f i l t e r p h a s e m a r gi n = 6 1 d e g r e e s . t h i s r e s u l t i s d i r e ct l y a ff e c t e d b y l o o p f i l t e r d e sign . f a s t e r s e t t l i n g t i m e i s p o s s i b l e w i t h wi de r l o o p f i l t e r b a n d wi d t h a n d l o w e r p h a s e m a r gi n . 12827-028 10 20 30 40 50 60 70 80 90 0 0.66 1.30 2.00 3.30 tuning vo lt age (v) kvco (mhz/v) 2.60 1587mhz 2013mhz 2854mhz tuning ca p 15 2453mhz 12827-029 ?200 ?150 ?100 ?50 0 50 100 150 200 phase error (degrees) time (s) 0 20 40 60 80 100 120 140 160 settling time t o < 10 degrees phase error 12827-030 ?200 ?150 ?100 ?50 0 50 100 150 200 phase error (degrees) time (s) 0 20 40 60 80 100 120 140 160 settling time t o < 10 degrees phase error note: loo p fi l ter bandwidth = 127khz, loo p fi l ter phase margin = 61 degrees. this resu l t is direct l y affected b y loo p fi l ter design. f aster settling time is possible with wider loo p fil ter bandwidth and lower phase margin. 12827-031 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 calibr a ted a t +85c, measured a t ?40c 1330 1710 1900 2090 2280 2470 2660 2850 3040 1520 tune vo lt age after calibr a tion (v) vco frequenc y (mhz) calibr a ted a t +27c, measured a t +27c calibr a ted a t ?40c, measured a t +85c calibr a ted a t +85c, measured a t +85c calibr a ted a t ?40c, measured a t ?40c 12827-032 f max f min rev. a | page 12 of 48
data sheet hmc832 figure 33 . current consumption in single - ended output configuration, output gain configured in vco_reg 0x07[3:0], differential or si ngle - ended mode programmed in vco_reg 0x03[3:2] figure 34 . reference input sensitivity, square wave, measured from a 50 source with a 100 external resistor termination figure 35 . mute mode isolation, measured at ou t put figure 36 . current consumption in differential output configuration, output gain configured in vco_reg 0x07[3:0], differential or single - ended mode programmed in vco_reg 0x03[3:2] figure 37 . reference input sensitivity, sinusoidal wave, measured from a 50 source with a 100 external resistor termination 160 170 180 190 200 210 220 230 240 current consumption (ma) output frequenc y (mhz) f o f o /2 f o /62 500 0 1000 1500 2000 2500 3000 high performance mode (vco_reg0x03[1:0] = 3d) low current consumption mode (vco_reg0x03[1:0] = 1d) f o /4 output gain 0db output gain 6db 12827-033 220 222 224 226 228 230 232 14mhz square w a ve 25mhz square w a ve 50mhz square w a ve 100mhz square w a ve fom (dbc/hz) ?12 ?9 ?6 ?3 0 3 ?15 reference power (dbm) 12827-034 ?1 10 ?90 ?70 ?50 ?30 ?10 1000 100 frquenc y (mhz) isol a tion (db) 3000 m u t e o n ( v c o _ r e g 0 x 0 3 [ 8 : 7 ] = 3 d ) sig na l o n r f _ n p i n w h e n r f _ n p i n o f f , r f _ p p i n o n ( v c o _ r e g 0 x 0 3[ 3 : 2 ] = 1 d ) , m u t e o f f ( o n o n l y d u ri n g v c o c a l i b r a t i o n v c o _ r e g 0 x 0 3 [ 8 : 7 ] = 1 d ) b o t h r f _ n a n d r f _ p p i n s o f f , ( v c o _ r e g 0 x 0 3[ 3 : 2 ] = 0 d ) , m u t e o f f ( o n o n l y d u ri n g v c o c a l i b r a t i o n v c o _ r e g 0 x 0 3 [ 8 : 7 ] = 1 d ) 12827-035 180 200 220 240 260 current consumption (ma) output frequenc y (mhz) f o f o /2 f o /4 f o /62 500 0 1000 1500 2000 2500 3000 output gain 0db output gain 6db high performance mode (vco_reg0x03[1:0] = 3d) low current consumption mode (vco_reg0x03[1:0] = 1d) 12827-036 200 205 210 215 220 225 230 235 ?20 ?15 ?10 ?5 0 5 14mhz sinusoida l 25mhz sinusoida l 50mhz square 100mhz square reference power (dbm) fom (dbc/hz) 12827-038 rev. a | page 13 of 48
hmc832 data sheet theory of operation figure 38 . pll and vco subsystems the hmc832 pll with i ntegra ted vco is comprised of two sub systems; pll subsystem and vco subsystem, as shown in figure 38. pll subsystem overvi ew the pll subsystem divides down the vco output to the desired comparison frequency via the n - divider (integer value set in re g ister 0x 03, fractional value set in reg ister 0x 04), compares the divided vco signal to the divided reference signal (reference divider set in reg ister 0x 02) in the phase detector (pd), and drives the vco tuning voltage via the charge pump (cp) (configured in reg ister 0x 09 ) to the vco subsystem. some of the additional pll subsystem functions include ? delta - s igma configuration (register 0x 06) . ? exact frequency mode ( c onfigured in register 0x 0c, register 0x 03, and register 0x 04) . ? lock d etect (ld) c onfiguration ( use register 0x 07 to configure ld and register 0x 0f to configure the ld_sdo output pin) . ? external cen pin used for the hardware pll enable pin. cen pin does not affect the vco subsystem. typically, only writes to the divider registers (integer part uses r egister 0x 03, fractional part uses register 0x 04) of the pll subsystem are required for hmc832 output frequency changes. divider registers of the pll subsystem ( register 0x 03 and register 0x 04), s et the fundamental frequency (1500 mhz to 3000 mhz) of the vco subsystem. output frequencies ranging from 25 mhz to 1500 mhz are generated by tuning to the appropriate fundamental vco frequency (1500 mhz to 3000 mhz) by programming the n divider ( register 0x 03 and register 0x 04 ) and programming the output divider (divide by 1/2/4/6 /60/62, in vco_reg 0x 02 ) in the vco subsystem. for detailed frequency tuning information and example, see the frequency tuning section . vco subsystem overvi ew the vco subsystem consists of a capacitor switched step tuned vco and an output stage. in typical operation, the vco subsystem is programmed with the appropriate capacitor switch setting that is executed automatically by the pll s ubsystem autocalibration state machine when a utocalibration is enabled ( register 0x 0a[11] = 0, see the vco calibration section for more information). the vco tunes to the fundamental frequency (1500 mhz to 3000 mhz ), and is locked by the cp output from the pll subsystem. the vco subsystem controls the output stage of the hmc832 enabling configuration of ? user defined performance settings ( see the programmable performance technology section ) that are configured via vco_reg 0x 03[1:0] . ? vco o utput divider settings that are configured in the vco_reg 0x 02 (divide by 2/4/6 60/62 to generate frequencies from 25 mhz to 1500 mhz, or divide by 1 to generate fundamental frequencies between 1500 mhz and 3000 mhz) . ? output gain settings ( vco_reg 0x 07[3:0]) . ? output return loss setti ng ( vco_reg 0x 03[5]). see figure 26 for more information. ? si ngle - ended or differential output operation ( vco_reg 0x 03[3:2]) . ? mute ( vco_reg 0x 03[8:7]) . spi (serial port int erface) configuratio n of pll and vco subsystems the two subsystems (pll subsystem and vco subsystem) have their own register maps as shown in the pll register map and vco subsystem register map sections. typically , writes to both register maps are required for initialization and frequency tuning operations. as shown in figure 38 , the pll subsystem is connected directly to the spi of the hmc832 , wh ereas the vco subsystem is connected indirectly through the pll subsyst em to the rf_n rf_ p vtune ref buff rf buffer en pll buff pll buff en vspi vspi ca l contro l 4 modul a t or charge pum p phase frequenc y detec t op r divider pll on l y xref p cen cp sen sdi sck ld_sdo n divider ca l vco en cntr l f o or n or 2 3 12827-043 rev. a | page 14 of 48
data sheet hmc832 rev. a | page 15 of 48 hmc832 spi. as a result, writes to the pll register map are written directly and immediately, whereas the writes to the vco subsystem register map are written to the pll subsystem register 0x05 and forwarded via the internal vco spi (vspi) to the vco subsystem. this is a form of indirect addressing. note that vco subsystem registers are write only and cannot be read. more information is available in the vco serial port interface (vspi) section. vco serial port interface (vspi) the hmc832 communicates with the internal vco subsystem via an internal 16-bit vco spi. the internal serial port controls the step tuned vco and other vco subsystem functions. note that the internal vco subsystem spi (vspi) runs at the rate of the autocalibration fsm clock, t fsm , (see the vco autocalibration section) where the fsm clock frequency cannot be greater than 50 mhz. the vspi clock rate is set by register 0x0a[14:13]. writes to the control registers of the vco are handled indirectly via writes to register 0x05 of the hmc832 . a write to hmc832 register 0x05 causes the internal pll subsystem to forward the packet, msb first, across its internal serial link to the vco subsystem, where it is interpreted. vspi use of register 0x05 the packet data written into register 0x05 is subparsed by logic at the vco subsystem into the following three fields: field 1bits[2:0]: 3-bit vco_id, target subsystem address = 000b. field 2bits[6:3]: 4-bit vco_regaddr, the internal register address inside the vco subsystem. field 3bits[15:7]: 9-bit vco_data, data field to write to the vco register. for example, to write 0_1111_1110 into register 2 of the vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to register 0x05 = 0_1111_1110b, 0010b, 000b or equivalently, register 0x05 = 7f10. during autocalibration, the autocalibration controller writes into the vco register address specified by the vco_id and vco_regaddr, as stored in register 0x05[2:0] and register 0x05[6:3], respectively. autocalibration requires that these values be zero (register 0x05[6:0] = 0); otherwise, when they are not zero (register 0x05[6:0] 0), autocalibration does not function. to ensure that the autocalibration functions, it is critical to write register 0x05[6:0] = 0 after the last vco subsystem write prior to an output frequency change triggered by a write to either register 0x03 or register 0x04. however, it is impossible to write only register 0x05[6:0] = 0 (vco_regaddr) without writing register 0x05[15:7] (vco_data). therefore, to ensure that the vco_data (register 0x05[15:7]) in vco_regaddr 0x00 is not changed, it is required to read the switch settings provided in regis- ter 0x10[7:0], and then rewrite th em to register 0x05[15:7], as shown in the following example: 1. read register 0x10 2. write to register 0x05 the following: a. register 0x05[15:14] = register 0x10[7:6] b. register 0x05[13] = 1, reserved bit c. register 0x05[12:8] = register 0x10[4:0] d. register 0x05[7:0] = 0 changing the vco subsystem configuration (vco subsystem register map section) without following this procedure results in a failure to lock to the desired frequency. for applications not using the read functionality of the hmc832 spi, in which register 0x10 cannot be read, it is possible to write register 0x05 = 0x0 to set register 0x05[6:0] = 0, which also sets the vco subband setting equal to zero (register 0x05[15:7] = 0), effectively programming incorrect vco subband settings and causing the hmc832 to lose lock. this procedure is then immediately followed by a write to: ? register 0x03, if in integer mode. ? register 0x04, if in fractional mode. this write effectively retriggers the autocalibration state machine, forcing the hmc832 to relock whether in integer or fractional mode. this procedure causes the hmc832 to lose lock and relock after every vco subsystem change. typical output frequency and lock time is shown in figure 27 and figure 30, and is typically in the order of 100 s for a phase settling of 10, and is also dependent on loop filter design (loop filter bandwidth and loop filter phase margin).
hmc832 data sheet vco subsystem figure 39 . pll and vco subsystems the hmc832 contains a vco subsystem that can be configured to operate in: ? fundamental freque ncy (fo) mode (1500 mhz to 3000 mhz). ? divide by n mode, where n = 2, 4, 6, 8 58, 60, 62 (25 mhz to 1500 mhz). all modes are vco register program mable , as shown in figure 39 . one loop filter design can be used for the entire frequency of operation of the hmc832 . vco calibration vco autocalibration the hmc832 uses a step tuned type vco. a simplified st ep tuned vco is shown in figure 41 . a step tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequenc y of the vco to be adjusted or stepped by switching in and out of the vco tank capacitors. note that more than one capacitor can be switched in at a time. a step tuned vco allows the user to center the vco on the re quired output frequency while keeping the varactor tuning voltage optimized near the mid voltage tuning point of the hmc832 charge pump. this enables the pll charge pump to tune the vco over the f ull range of operation with both a low tuning voltage and a low tuning sensitivity (k vco ). the vco switches are normally controlled automatically by the hmc832 using the autocalibration feature. t he autocalibration feature is implemented in the internal state machine. it manages the selection of the vco subband (capacitor selection) when a new frequency is programmed. the vco switches may also be controlled directly via register 0x 05 for testing or for other special purpose operation s . other control bits specific to the vco are also sent via register 0x 05. to use a step tuned vco in a closed loop, the vco must be calibrated such that the hmc 832 knows which switch position on the vco is optimum for the desired output frequency. the hmc832 supports autocalibration of the step tuned vco. the autocalibration fixes the vco tuning voltage at the optimum midpoint of the charge pump output, then measures the free running vco frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase - locked frequency. this procedure result s in a phase - locked oscillator that locks over a narrow voltage range on the varactor. a typical tuning curve for a step tuned vco is shown in figure 40 . note that the tuning voltage stays in a narrow range over a wide range of output frequencies. spi ld_sdo vco_reg0x01[0] vco_reg0x01[3] en en 1, 2, 4, 6, ... 62 vco_reg0x01[2] vco_reg0x01[1], en vco_reg0x00[8:1] vco_reg0x00[0] loo p fi l ter vco vco ca l volt age en vco_reg0x07[3:0] vco_reg0x02[5:0] vco contro l vspi vtune rf_n rf_ p vdd master enable vco subsystem vco_reg0x03[1:0] vco_reg0x03[3] vco_reg0x03[2] vco_reg0x01[5] vco subsystem performance tuning contro l modul a t or n divider cp phase frequenc y detec t or charge pum p r divider xref p ca l 12827-044 rev. a | page 16 of 48
dat a sheet hmc832 figure 40 . typical vco tuning voltage after calibration the calibration is normally run automatically , once for every change of frequency. this ensures optimum selection of vco switch settings vs . time and temperature. the user does not normally need to be concerned about which switch setting is used for a given frequency because this is handled by the autocalibration routine. the accuracy required in the calibration affects the amount of time re quired to tune the vco. the calibration routine searches for the best step setting that locks the vco at the current programmed frequency and ensures that the vco stays locked and perform s well over its full temperature range without additional calibration , regardless of the temperature at which the vco was calibrated. autocalibration can also be disabled , thereby allowing manual vco tuning. refer to the manual vco calibration for fast frequency hopping section for a description of manual tuning . figure 41 . simplified step tuned vco 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1330 1520 1900 2090 3040 2850 2660 2470 2280 1710 tune vo lt age after calibr a tion (v) vco frequenc y (mhz) calibr a ted a t +8 5 c, measured a t +8 5 c calibr a ted a t +8 5 c, measured a t ?4 0 c calibr a ted a t ?40c, measured a t ?4 0 c calibr a ted a t ?40c, measured a t +85c calibr a ted a t +27c, measured a t +27c 12827-046 f min f max host sck synthesizer sdi c p vco rf out vco sub-band select vco vspi loo p fi l ter vcoi p vtune dtune vsck vsdo vsle sen 12827-045 rev. a | page 17 of 48
hmc832 data sheet autocalibration using register 0x05 autocalibration transfers switch control data to the vco subsystem via register 0x 05. the address of the vco subsystem in register 0x 05 is not altered by the autocalibration routine. the address and id of the vco subsystem in register 0x 05 must be set to the correct value before autocalibration is executed. for more information see the vco serial port interface (vspi) section . auto matic r e l ock on lock detect failure it is possible by setting register 0x 07[13] to have the vco subsystem automatically rerun the calibration routine and relock itself if lock detect indicates an unlocked condition for any reason. with this option the system attempt s to re l ock only once. vco autocalibration on frequency change assuming register 0x 0a[11] = 0, the vco calibration starts automatically whenever a frequency change is requested. if it is desired to rerun the autocalibration routine for any reason at the same frequency, rewrite the frequency change with the same value and the autocalibration routine execute s again without changing the final frequency. vco autocalibration time and accuracy the vco frequency is counted for t mmt , the period of a single autocalibration measurement cycle. t mmt = t xtal r 2 n (1) where: n is set by register 0x 0a[2:0] and results in measurement periods which are multiples of the pd period, t xtal r . r is the reference pat h division ratio currently in use, register 0x 02. t xtal is the period of the external reference (crystal) oscillator. the vco autocalibration counter , on average, expect s to register n counts, rounded down (floor) to the nearest integer, for every pd cycl e. n is the ratio of the target vco frequency, f vco , to the frequency of the pd, f pd , where n can be any rational number supported by the n divider. n is set by the integer ( n int = register 0x 03) and fractional (n frac = register 0x 04) register contents by equation 2. n = n int + n frac /2 24 (2) the autocalibration state machine and the data transfers to the internal vco subsystem spi (vspi) run at the rate of the fsm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. t fsm = t xtal 2 m (3 ) where m is 0, 2, 4 , or 5 as determined by register 0x 0a[14:13] . the expected number of vco counts, v, is given by v = floor ( n 2 n ) (4) the nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r ) (5) where the worst case measuremen t error, f err , is f err f pd / 2 n + 1 (6) a 5 - bit step tuned vco, for example, nominally requires five measurements for calibration or in the worst case , six measurements, and hence , seven vspi data transfers of 20 clock cycles each. the measurement has a programmable number of w ait states, k, of 128 fsm cycles defined by register 0x 0a[7:6] = k. total calibratio n time, worst case, is given by t cal = k 128 t fsm + 6 t pd 2 n + 7 20 t fsm (7) or equivalently t cal = t xtal (6 r 2 n + (140+( k 128)) 2 m ) (8) for guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8 th the frequency step caused by a vco subband switch change. better resolution settings show no improvement. figure 42 . vco calibration table 7 . autocalibration example with f xtal = 50 mhz, r = 1, m = 0 control value register 0 x 0 a 20 n 2 n t mmt (s) t cal (s) f err maximum 0 0 1 0.02 4.92 25 mhz 1 1 2 0.04 5.04 12.5 mhz 2 2 4 0.08 5.28 6.25 mhz 3 3 8 0.16 5.76 3.125 mhz 4 5 32 0. 64 8.64 781 khz xref calibr a tion window reg0x02 s t art v vco ctr fsm 50mhz max for fsm + vspi clocks rega[14:13] m = [0, 2, 4, 5] rega[2:0] n = [0, 1, 2, 3, 5, 6, 7, 8] s t o p t mmt = rt x t al 2 n 12827-047 t pd 2 n 2 m r rev. a | page 18 of 48
dat a sheet hmc832 control value register 0 x 0 a[ 2:0 ] n 2 n t mmt (s) t cal (s) f err maximum 5 6 64 1.28 12.48 390 khz 6 7 128 2.56 20.16 95 khz 7 8 256 5.12 35.52 98 khz vco autocalibration example the vco subsystem must satisfy the maximum f pd limited by the two following conditions: n 16 ( f int ), n 20.0 ( f frac ) where n = f vco / f pd . f pd 100 mhz for example, if the vco subsystem output frequency is to operate at 2.01 ghz and the crystal frequency is f xtal = 50 mhz, r = 1, and m = 0 ( see figu re 42 ), then t fsm = 20 ns (50 mhz). note that when using autocalibration , the maximum autocali - bration finite state machine (fsm) clock cannot exceed 50 mhz (see register 0x 0a[14:13]). the fsm clock does not affect the accuracy of the measurement, it onl y affects the time to produce the result. this same clock is used to clock the 16 - bit vco serial port. if time to change frequencies is not a concern, then the calibration time for maximum accuracy can be set , and therefore , the measurement resolution is o f no concern. using an input crystal of 50 mhz (r = 1 and f pd = 50 mhz) the times and accuracies for calibration using equation 6 and e quation 8 are listed in table 7 , w here minimal tuning time is 1/8 th of the vco band spacing. across all vcos, a measurement resolution better than 800 khz produce s correct results. set ting m = 0 and n = 5, provides 781 khz of resolution and adds 8.6 s of autocalibration time to a normal frequency hop. after the autocalibration sets the final switch value, 8.64 s after the frequency change command, the fractional register is loaded, and the loop lock s with a normal tran sient predicted by the loop dynamics. therefore, as shown in this example , autocalibration typically adds about 8.6 s to the normal time to achieve frequency lock. use autocalibration for all but the most extreme frequency hopping requirements. manual vco calibration for fast frequency hopping when switch ing frequencies quickly is needed, it is possible to eliminate the autocalibration time by calibrating the vco in advance and storing the switch number vs . frequency infor - mation in the host. this is accom plished by initially locking the hmc832 on each desired frequency using autocalibration , then reading and storing the selected vco switch settings. the vco switch settings are available in registe r 0x 10[7:0] after every autocalibration operation. the host must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers whe n autocalibration is disabled. therefore, frequency changes with manual control and autocalibration disabled requires a minimum of two serial port transfers to the pll, once to set the vco switches and once to set the pll frequency. when autocalibration is disabled , register 0x 0a[11] = 1, the vco update s its registers immediately with the value written via register 0x 05. the vco internal transfer requires 16 vsck clock cycles after the completion of a write to register 0x 05. vsck and the autocalibration con troller clock are equal to the input reference divided by 0, 4, 16 , or 32 as controlled by register 0x 0a[14:13]. registers required for frequency changes in fractional mode in fractional mode (register 0x06[11] = 1), a large change of frequency may require main serial port writes to one of the three following registers ? t he integer register , intg , register 0x 03 . this is required only if the integer part changes . ? t he vco spi register, register 0x 05. this is required only for manual control of vco if register 0x 0a[11] = 1, autocalibration is disabled , or to change the vco output divider value ( vco_reg 0x 02), see figure 39 for more information . ? t he fractional register, register 0x 04. the fractional register write trigger s a utocalibration when register 0x 0a[11] = 0, and it is loaded into the modulator automatically after the a utocalibration runs. if a utocalibration is disabled, regis - ter 0x 0a[11] = 1, the fractional frequency change is loaded immediately into the modulator when the register is written with no adjustment to the vco. small steps in frequency in fractional mode, with a utocalibration enabled ( register 0x 0a[11] = 0), usually require only a single write to the fractional register. in a w orst - case scenario , three main serial port transfers to the hmc832 could be required to change frequencies in fractional mode. if the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. in all cases, in frac - tional mode, it is necessary to write to the fractional register , register 0x 04, for frequency changes. rev. a | page 19 of 48
hmc832 data sheet registers required for frequency changes in integer mode in integer mode (register 0x06[11] = 0 ), a chan ge of frequency requires main serial port writes to the following registers: ? vco spi register, register 0x 05 . this is required for manual control only of the vco when register 0x 0a[11] = 1 ( a utocalibration disabled) or when the vco output divider value must change (vco_reg 0x02). ? i nteger register , register 0x 03. i n integer mode, an integer register write triggers a utocalibration when register 0x 0a[11] = 0 and it is loaded into the prescaler automatically after a utocalibration runs. if a utocalibrati on is disabled, register 0x 0a[11] = 1, the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the vco. normally , changes to the integer register cause large steps in the vco frequency ; therefore, the vco sw itch settings must be adjusted. autocalibration enabled is the recommended method for integer mode frequency changes. if a uto - calibration is disabled ( register 0x 0a[11] = 1), a priori knowledge of the correct vco switch setting and the corresponding adjust ment to the vco is required before executing the integer frequency change. vco output mute function the hmc832 features an intelligent output mute function with the capability to disable the vco o utput while maintaining fully functional pll and vco subsystems . the mute function is automatically controlled by the hmc832 and provides a number of mute control options including ? automatic mut e. this option automatically mutes the outputs during vco calibration during output frequency changes. this mode can be useful in eliminating any out of band emissions during frequency changes, and ensuring that the system emits only the desired frequencies. it is enabled by writing vco_reg 0x 03[8:7] = 1d. ? always mute ( vco_reg 0x 03[8:7] = 3d). this mode is used for manual mute control. typical isolation when the hmc832 is muted is alw ays better than 50 db, and is ~ 40 db better than disabling the individual outputs of the hmc832 via vco_reg 0x 03[3:2] , as shown in figure 35. also note that the vco subsy stem registers are not directly accessible. they are written to the vco subsystem via pll register 0x 05. see figure 39 and the vco serial port interface (vspi) section for more information about the vco subsystem spi. vco built - i n test (bist) with autocalibration the frequency limits of the vco can be measured using the bist features of the a utocalibration machine by setting regis - ter 0x 0a[10] = 1 , which freezes the vco s witches in one position. vco switches may then be written manually with the varactor biased at the nominal midrail voltage used for a utocalibration . for example , to measure the vco maximum frequency use s witch 0, written to the vco subsystem via register 0 x 05 = 000000001 0000 vco _ id , where vco _ id = 000 b. when a utocalibration is enabled ( register 0x 0a[11] = 0), and a new frequency is written, a utocalibration r un s . the vco frequency error relative to the command frequency is measured and the results are writ ten to register 0x 11[19:0] , where register 0x 11[19] is the sign bit. the result is written in terms of vco count error ( see equation 4). for example , if the expected vco is 2 ghz, the reference is 50 mhz, and n is 6, expect to measure 2000/(50/2 6 ) = 2560 counts. if a difference of ? 5 counts is measured in register 0x 11, then it means 2555 counts were actually measured . hence , the actual frequency of the vco is 5/2560 low, or 1.99609375 ghz, 1 c ount ~ 781 khz. pll subsystem charge pump (cp) and phase dete ctor (pd) the p hase detector (pd) has two inputs, one from the reference path divider and one from the rf path divider. when in lock , these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each o ther. t he frequency of operation of the pd i s f pd . most formulae related to step size, - modulation, timers , and so forth are functions of the operating frequency of the pd, f pd . f pd is also referred to as the comparison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians ( 360 ) of input phase difference. charge pump a simplified diagram of the charge pump is shown in figure 43. the cp consists of four programmable current sources, two con - trolling the cp g ain (up gain register 0x 09[13:7], and down gain register 0x 09[6:0]) and two controlling the cp o ffset, where the magnitu de of the offset is set by register 0x 09[20:14], and the direction is selected by register 0x 09[21] = 1 for up and register 0x 09[22] = 1 for down offset. cp g ain is used at all times, wh ereas cp o ffset is recommended for fractional mode of operation only . typically , the cp u p and d own gain settings are set to the same value ( register 0x 09[13:7] = register 0x 09[6:0]). rev. a | page 20 of 48
dat a sheet hmc832 charge pump gain charge pump u p and d own gains are set by register 0x 09[6:0] and register 0x 09[13:7] , respectively. the current gain of the pump in a mps/radian is equal to the gain setting of this register ( register 0x09 ) divided by 2 . typical cp gain setting is set to 2 ma to 2.5 ma ; however , lower values can also be used. note that v alues less than 1 ma may result in degraded phase noise performance. for example, if both register 0x 09[13:7] and register 0x 09 [6:0] are set to 50 decimal, the output current of each pump is 1 ma , and the phase frequency detector ga in is k p = 1 ma/2 radians, or 159 a/rad. see the charge pump (cp) and phase detector (pd) section for more information. figure 43 . charge pump gain and offset control up pd ref pa th vco pa th loo p fi l ter up gain reg0x09[13:7] up offset reg0x09[21] 0 a t o 635 a 5 a ste p reg0x09[20:14] dn offset reg0x09[22] 0 a t o 635 a 5 a ste p reg0x09[20:14] 0m a t o 2.54m a 20 a ste p 0m a t o 2.54m a 20 a ste p dn gain reg0x09[6:0] dn 12827-048 rev. a | page 21 of 48
hmc832 data sheet charge pump phase offset in integer mode , the phase detector operates with zero offset. the divided reference signal and the divided vco signal arrive at the phase detector input s at the same time. integer mode does not require any cp o ffset current. when operating in integer mode, disable cp offset in both directions ( up and down) by writing register 0x 09[22:21] = 00 b , and set the cp o ffset magnitude to zero by writing register 0 x 09[20:14] = 0 . in fractional mode, cp linearity is o f paramount importance. any non linearity degrades phase noise and spurious perfor - mance. t hese nonlinearities are eliminated by operating the pd with an average phase offset, either positive or negative (either the reference or the vco edge always arrives first at the pd , that is, leads). a programmable cp offset current source is used to add dc current to the loop filter and to create the desired phase offset. positive current causes the vco to lead, neg ative current causes the reference to lead. the c p offset is controlled via register 0x 09. the phase offset is scaled from 0 to 360 , where they arrive a full cycle late. the specific level of charge pump offset current ( register 0x 09, bits [20:14] ) is pr ovided in equation 9 and plotted in figure 44. required cp offset = min [(4.3 10 ?9 f pd i cp ), 0.25 i cp ] (9) where: f pd is the c omparison frequency of the phase dete ctor (hz) . i cp is the full - scale current setting (a) of the switching charge pump (set in register 0x 09[6:0] and register 0x 09[13:7]) . figure 44 . recommended cp offset current vs . pd f requency for t ypical cp gain currents, calculated u sing equation 9 do not allow t he required cp offset current to exceed 25 % of the programmed cp current. it is recommended to enable the u p o ffset and disable the down offset by writing register 0x 09, bits [22:21] = 01 b. operation with cp offset influences the required configuration of the lock detect function. see the description of the lock detect function in the lock detec t section . phase detector functions register 0x0b, the p hase detector register , allows manual access to control special phase detector features. setting register 0x 0 b[ 5 ] = 0 masks the pd up output, which prevents the charge pump from pumping up. setting r egister 0x 0 b[ 6 ] = 0 , masks the pd down output, which prevents the charge pump from pumping down. clearing both register 0x 0b[5] and register 0x 0 b[ 6 ] tristates the charge pump while leaving all other functions operating internally. pd f orce up ( register 0x 0 b[9] = 1 ) and pd f orce down ( register 0x 0b[10] = 1 ) allows the charge pump to be forced up or down , respectively. this forces the vco to the ends of the tu n ing range, which is useful in testing the vco. reference input stage figure 45 . reference path input stage the reference buffer provides the path from an external reference source (generally crystal - based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation controlled by register 0x 08[2 1]. high g ain ( regis - ter 0x 08[21] = 0) is recommended below 200 mhz, and h igh frequency ( register 0x 08[21] = 1) for 200 mhz to 350 mhz operation. the buffer is internally dc biased with 100 internal termination. for a 50 match, add an ex ternal 100 r esistor to ground followed by an ac coupling capacitor (impedance less than 1 ). at low frequencies, a relatively square reference is recommended to maintain a high input slew rate . at higher frequencies, use a square or sinusoid . table 8 shows the recommended operating regions for different reference frequencies. if operating outside these regions , the device usually still operate s , but with degraded reference path phase noise performance. when operating at 50 mh z, the i nput referred phase noise of the pll is between ? 148 dbc/hz and ? 150 dbc/hz at a 10 khz offset , depending upon the mode of operation. to avoid degra - dation of the pll noise contribution, t he input reference signal should be 10 db better than this floor . n ote that such low levels are only necessary if th e pll is the dominant noise contributor and these levels are required for the system goals. 0 100 200 300 400 500 600 700 0 20 40 60 80 100 recommended offset current (a) phase detec t or frequenc y (mhz) cp current = 2.5m a cp current = 2m a cp current = 1m a 12827-049 xref p 80 v b 20 ac couple 100 r vdd 12827-050 rev. a | page 22 of 48
dat a sheet hmc832 table 8 . reference sensitivity reference input frequency (mhz) square input sinusoidal input slew > 0.5 v/ns recommended swing (v p - p ) recommended power range (dbm) recommended min imum max imum recommended min imum max imum < 10 yes 0.6 2.5 no no no 10 y es 0.6 2.5 no no no 25 y es 0.6 2.5 okay 8 15 50 y es 0.6 2.5 y es 6 15 100 y es 0.6 2.5 y es 5 15 150 okay 0.9 2.5 y es 4 12 200 okay 1 . 2 2.5 y es 3 8 ref erence path, r divider t he reference path, r divider is based on a 14 - bit counter and can divide input signals by values from 1 to 16,383 and is controlled via register 0x 02. rf path , n divider the main rf path divider is capable of av erage divide ratios between 2 19 ? 5 (524,283) and 20 in fractional mode, and 2 19 ? 1 (524,287) to 16 in integer mode. the vco frequency range divided by the minimum n divider value place s practical restrictions on the maximum usable pd frequency. for example , a vco operating at 1.5 ghz i n fractional mode with a minimum n divider value of 20 has a maximum pd frequency of 75 mhz. lock detect the lock detect (ld) function verifies that the hmc832 is generating the desired frequency. it is enabled by writing register 0x 07[3] = 1. the hmc832 provides an ld indicator in one of two ways ? as an output available on the ld_sdo pin of the hmc832 , ( c onfiguration is required to use the ld_sdo pin for ld purpose s , for more information , see the serial port and configuring the ld_sdo pin for ld outp ut section s). ? or reading from register 0x 12[1] , where bit 1 = 1 indicates a locked condition and bit 1 = 0 indicates an unlocked condition. the ld circuit expects the divided vco edge and the divided reference edge to appear at the pd within a user specif ied time period (window), repeatedly. either signal may arrive first, only the difference in arrival times is significant. the arrival of the two edges within the designated window increments an internal counter. when the count reaches and exceeds a user s pecified value ( register 0x 07[2:0]) the hmc832 declares lock. failure in registering the two edges in any one window resets the counter and immediately declares an unlocked condition. lock is deem ed to be reestablished when the counter reaches the user specified value ( register 0x 07[ 2:0 ]) again. the hmc832 supports two lock detect modes: ? analog ld, that only supports a fixed window size o f 10 ns. analog ld mode is selected by writing register 0x 07[6] = 0. ? digital ld, that supports a user configurable window size, programmed in register 0x 07[11:7]. digital ld is selected by writing register 0x 07[ 6 ] = 1 . lock detect configuration optimal spe ctral performance in fractional mode requires cp current and cp offset current configuration discussed in detail in the charge pump (cp) and phase detector (pd) section . these settings in register 0x 09 impact the r equired ld window size in fractional mode of operation. to function, the required lock detect window size is provided by e quation 10 in fractional mode and equation 11 in integer mode . ld window (sec) = 2 ) hz ( 1 (sec) 10 66 . 2 (a) (hz) (a) 9 ? ? ? ? ? ? ? ? + + ? (10) pd f sec window ld = 2 1 ) ( (1 1) where: f pd is the comparison frequency of the phase detector. i cp offset is the charge pump offset current (register 0 x 09[ 20:14 ]). i cp is the full - scale current setting of the switching charge pump (register 0 x 09[ 6:0 ] or register 0 x 09[ 13:7 ]). if the res ult provided by equation 10 is equal to 10 ns , a nalog ld can be used (register 0x07[6] = 0) ; o therwise , d igital ld is necessary ( register 0x07[6] = 1 ) . table 9 lists the required register 0x07 settings to appropria tely program the digital ld window size. from table 9 , select the closest value in the digital ld window size columns to the ones calculated in equation 10 and equation 11, and program register 0x07[11:10] and regi ster 0 x 07[ 9:7 ] accordingly. rev. a | page 23 of 48
hmc832 data sheet table 9 . typical digital lock detect window ld timer speed register 0x07 bits[11:10] digital lock detect window size nominal value (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 7.1 9.2 13.3 22 38 72 138 272 slowest 11 7.6 10.2 15 .4 26 47 88 172 338 ld timer divide setting register 0x07 , bits [9:7] 000 001 010 011 100 101 110 111 digital window configuration example assuming, fractional mode, with a 50 mhz pd and a ? char ge pump gain of 2 ma (register 0 x 09[ 13:7 ] = 0 x 64, register 0 x 09[ 6:0 ] = 0 x 64), ? up offset (register 0 x 09[ 22:21 ] = 01b) ? offset current magnitude of + 400 a (register 0 x 09[ 20:14 ] = 0 x 50) applying equation 10, the required ld window size is: ld window (sec) = ns 33 . 13 2 ) hz ( 10 50 1 (sec) 10 66 . 2 ) a ( 10 2 ) hz ( 10 50 ) a ( 10 4 . 0 6 9 3 6 3 = ? ? ? ? ? ? ? ? + + ? ? ? configuring the ld_sdo pin for ld output setting register 0x 0f[7] = 1 and register 0x 0f[4:0] = 1 display s the lock detect flag on the ld_sdo pin of the hmc832 . w hen locked, ld_sdo is high. as the name suggests, ld_sdo pin is multiplexed between the ld and the serial data output ( sdo ) signals. therefore, ld is available on the ld_sdo pin at all times except when a serial port read is requested, in which case the pi n reverts temporarily to the serial data output pin, and returns to the lock detect flag after the read is completed. ld can be made available on ld_sdo pin at all times by writing register 0x 0f[6] = 1. in that case , the hmc832 does not provide any readback functionality because the sdo signal is not available. cycle slip prevention (csp) when changing vco frequency and the vco is not yet locked to the reference, the instantaneous frequencies of th e two pd inputs are different, and the phase difference of the two inp uts at the pd varies rapidly over a range much greater than 2 radians. because the gain of the pd varies linearly with phase up to 2 , the gain of a conventional pd cycle s from high gain, when the phase difference approaches a multiple of 2, to low gai n, when the phase difference is slightly larger than a multiple of 0 radians. the output current from the charge pump cycle s from maximum to minimum , even though the vco has not yet reached its final frequency. the charge on the loop filter small cap acitor may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency reverse temporarily during locking. this phenomen on is known as cycle slipping. cycle slipping causes the pull - in rate during the locking phase to va ry cyclically. cycle s lipping increases the time to lock to a value greater than that predicted by normal small signal laplace transform analysis. the hmc832 pd features an ability to reduce cycle slipping during acquisition. the cycle slip prevention (csp) feature increases the pd gain during large phase errors. the specific phase error that triggers the momentary increase in pd gain is set via register 0x 0b[8:7] . frequency tuning the hmc832 vco subsystem always operates in fundamental frequency of operation (1500 mhz to 3000 mhz). the hmc832 generates frequencies below its fundam ental frequency (25 mhz t o 1500 mhz) by tuning to the appropriate fundamental frequency and selecting the appropriate ou tput d ivider setting (divide by 2/4/6 / 60/62) in vco_reg 0x 02[ 5:0 ]. the hmc 832 automatically controls frequency tuning in the fundamental band of operation, for more information see the vco autocalibration section . to tune to frequencies below the fundamental frequency range (<1500 mhz) it is required to tune the hmc832 to the appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6 / 60/62) in vco_reg 0x 02[ 5:0 ]. integer mode the hmc832 is capable of operating in integer mode. for i nteger mode , set the following registers : ? disable the fractional modulator , register 0x 06[11] = 0 ? bypass the m odulator circuit, register 0x 06[7] = 1 in integer mode , the vco step size is fixed to that of the pd frequency. integer mode typically has a 3 db lower phase noise than fractional mode for a given pd operating frequency. integer mode, however, often requires a lower pd frequency to meet ste p size requirements. the fractional mode advantage is that higher pd frequencies can be used ; therefore, lower phase noise can often be realized in fractional mode. disable c harge p ump offset when in integer mode. rev. a | page 24 of 48
dat a sheet hmc832 integer frequency tuning in integer mode the digital - modulator is shut off and the n divider ( register 0x 03) may be programmed to any integer value in the range of 16 to 2 19 ? 1. to run in integer mode , configure register 0x 06 ( as described in the inte ger mode section) , then program the integer portion of the f requency as explained by equation 1 2 , ignoring the fractional part. 1. disable the fractional modulator, register 0x 06[11] = 0 2. bypass the - modulator register 0x 06[7] = 1 3. to tune to frequencies ( <1500 mhz), select the appropriate output divider value vco_reg 0x 02[5:0]. writing to vco subsystem registers ( vco_reg 0x02 [5:0] and vco_reg 0x03 [0] in this case) is accomplished indirectly through pll r egister 5 ( register 0x 05). more information on commun i - cating with the vco subsystem through pll register 0x 05 is available in the vco serial port interface (vspi) section. fractional mode the hmc832 is plac ed in fractional mode by setting the following registers: ? enable the fractional modulator , register 0x 06[11] = 1 . ? connect the - modulator in circuit, register 0x 06[7] = 0 . fractional frequency tuning this is a generic example, with the goal of explaining how to program the output frequency. actual variables are dependant upon the reference in use. the hmc832 in fractional mode can achieve frequencies at fractional multiples of the reference. the frequency of the hmc832 , f vco , is given by frac int frac int xtal vco f f n n r f f + = + = ) ( (12) f out = f vco / k (13) w here: f out is the output frequency after any potential dividers. k is 1 for fundamental, or k = 2, 4, 6, 5 8, 60, 62 depending on the selected output divider value ( register 0x 05[5:0] indirectly to vco_reg 0x 02[5:0]) . n int is the integer division ratio, register 0x 03, an integer number between 20 and 524,284 . n frac is the fractional part, from 0.0 to 0.99999 ..., n frac = register 0x 04/2 24 . r is the reference path division ratio, register 0x 02. f xtal is the frequency of the reference oscillator input . f pd is the pd operating frequency, f xtal /r . for example: f out = 1402.5 mhz k = 2 f vco = 2,805 mhz f xtal = 50 mhz r = 1 f pd = 50 mhz n int = 56 n frac = 0.1 register 0x 04 = round(0.1 2 24 ) = round(1 ,677, 721.6) = 1 ,677,722. error z f vco hz 192 . 1 mh 2805 2 1677722 56 1 10 50 24 6 + = ? ? ? ? ? ? + error f f vco out hz 596 . 0 mhz 5 . 1402 2 + = = exact frequency tuning due to quant ization effects, the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example, a 24 - bit fractional modulator has frequency resolutio n set by the phase detector (pd ) compari - son rate divided by 2 24 . the value 2 24 in the denominator is sometimes referred to as the modulus. analog devices plls use a fixed modulus , which is a binary number. in some types of fractional plls the modulus is variable, allowing exact frequency steps to be ach ieved with decimal step sizes. unfortunately , small steps using small modulus values result in large spurious outputs at multiples of the modulus period (channel step size). for this reason , analog devices plls use a large fixed modulus. normally, the step size is set by the size of the fixed modulus. in the case of a 50 mhz pd rate, a modulus of 2 24 would result in a 2.98 hz step resolution , or 0.0596 ppm. in some applications it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tolerated. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary ( for example, n = 50.0, 50.5, 50.25, 50.75 , and so forth ). note that , some common frequencies cannot be exactly repre sented. for example, n frac = 0.1 = 1/10 mus t be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. at f pd = 50 mhz , this rev. a | page 25 of 48
hmc832 data sheet translates to a 1.2 hz error. the exact frequency mode of the hmc832 ad dresses this issue and can eliminate quantization error by programming the channel step size to f pd /10 in register 0x 0c to 10 (in this example). more generally, this feature can be used whenever the desired frequency, f vco , can be exactly represented on a step plan where there are an integer number of steps (<2 14 ) across integer - n boundaries. mathematically, this situation is satisfied if ? ? ? ? ? ? = = 14 1 2 and ) , ( where 0 ) mod( pd gcd pd vco gcd gcd vcok f f f f gcd f f f 1 w ere gcd means greatest common divisor. f pd = frequency of the phase detector. f vcok is t he channel step frequenc y where 0 < k < 2 24 ? 1, a s shown in figure 46. some fractional plls are able to achieve these exact frequencies by adjusting (shortening) the length of the phase accumulator (the denominator or the modulus of the - modulator) so that the - modulator phase accumulator repeats at an exact period related to the interval frequency (f vcok ? f vco(k ? 1) ) in figure 46 . consequently, the shortened accumulato r results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok ? f vco(k ? 1) . for example, in some applications, these intervals might represen t the spacing between radio channels, with the spurious occur ring at multiples of the channel spacing. in comparison, the analog devices method is able to generate exact frequencies between adjacent integer - n boundaries while still using the full 24 - bit ph ase accumulator modulus, thus achieving exact frequency steps with a high phase detector c omparison rate, which allows analog devices plls to maintain excellent phase noise and spurious performance in the exact frequency mode . figure 46 . exact frequency tuning integer bounda r y integer bounda r y f n + 1 ? f n = f pd f n f vco1 f vco2 f vco3 f vco = f vco2 f vco4 f n + 1 f vco 14 f vco 14 ? 1 f vco 14 ? 2 12827-051 rev. a | page 26 of 48
data sheet hmc832 using exact frequency mode if the constraint in equation 16 is satisfied, the hmc832 is able to generate signals with zero frequency error at the desired vco fr equency. exact frequency mode can be re configured for each target frequency, or be setup for a fixed f gcd that applies to all channels. configuring exact frequency mode for a particular frequency 1. calculate and program the integer register setting register 0x03 = n int = floor ( f vco / f pd ) where the floor function is the rounding down to the nearest integer. 2. then calculate the integer boundary frequency f n = n int f pd . 3. calculate and program the exact frequency register value register 0x0c = f pd / f gcd where f g cd = gcd ( f vco ,f pd ). 4. calculate and program the fractional register setting register 0x04 ? ? ? ? ? ? ? ? ? = pd n vcok frac f f f ceil n ) ( 2 24 where ceil is the ceiling function meaning r ound up to the nearest integer. example: t o configure the hmc832 for exact frequency mode at f vco = 2800.2 mhz , where the pd rate (f pd ) = 61.44 mhz , p roceed as follows: 1. check equation 16 to confirm that the exact frequency mode for this f vco is possible. ? ? ? ? ? ? = 14 2 ) , ( pd gcd pd vco gcd f f and f f gcd f f gcd = gcd (2800.2 10 6 , 61.44 10 6 ) = 120 10 3 > 14 6 2 10 44 . 61 calculate n int n int = register 0x03 = d 2 x 0 d 45 10 44 . 61 10 2 . 2800 6 6 1 = = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? floor f f floor pd vco 3 calculate the value for register 0 x 0 c register 0x0c = 00 xc 0 d 3072 20000 10 44 . 61 ) 10 44 . 61 , 10 100 ( 10 44 . 61 ) ), (( 6 6 3 6 1 = = = = ? + gcd f f f gcd f pd vcok vcok pd 4 to program register 0x04, the closest integer - n boundary frequency (f n ) that is less than the desire d vco frequency (f vco ) must be calculated: f n = f pd n int . using the current example f n = f pd n int = 45 61.44 10 6 = 2764.8 mhz, then register 0x04 = 938000 x 0 d 9666560 10 44 . 61 ) 10 8 . 2764 10 2 . 2800 ( 2 ) ( 2 6 6 6 24 24 = = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ceil f f f ceil pd n vco exact frequency channel mode when multiple, equally spaced, exact frequency channels are needed that fall within the same interval ( that is, f n f vcok < f n + 1 ) where f vcok is shown in figure 46 and 1 k 2 14 , it is possible to maintain the same integer - n ( register 0x 03) and exact frequ ency register ( register 0x 0c) settings and only update the fractional register ( register 0x 04) setting. the exact frequency channel mode is possible when equation 16 is satisfied for at least two equally spaced adjacent frequency channels, that is, the cha nnel step size. to configure the hmc832 for exact frequency channel mode , initially and only at the beginning, the i nteger ( register 0x 03) and exact frequency ( register 0x 0c) registers need to be programmed for the smallest f vco frequen cy (f vco1 in figure 46 ), as follows: 1. calculate and program the integer register setting regis - ter 0x 03 = n int = floor(f vco1 /f pd ), where f vco1 is shown in figure 46 and corresponds to the minimum channel vco frequency. then , the lower integer boundary frequency is given by f n = n int f pd . 2. calculate and program the exact frequency register value register 0x 0c = f pd /f gcd , where f gcd = gc d ((f vcok + 1 ? f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing and the pd frequency ((f vcok + 1 ? f vcok ) and f pd ). rev. a | page 27 of 48
hmc832 data sheet t o switch between various equally spaced intervals (channels) only the fractional register ( register 0x 04) needs to be programmed to the desired vco channel frequency ( f vcok ) in the following manner: register 0x 04 = ? ? ? ? ? ? ? ? ? = pd n vcok frac f f f ceil n ) ( 2 24 where f n = floor( f vco1 / f pd ), and f vco1 , as shown in figure 46, represents the smallest channel vco frequency that is greater than f n . example: t o configure the hmc832 for the exact frequency mode for equally spaced intervals of 100 khz , where the first channel (channel 1) = f vco1 = 2800.200 mhz and the pd rate (f pd ) = 61.44 mhz, proceed as follows: 1. c heck that the exact frequency mode for this f vco1 = 2800.2 mhz (channel 1) and f vco2 = 2800.2 mhz + 100 khz = 2800.3 mhz (channel 2 ) is possible. ? ? ? ? ? ? = ? ? ? ? ? ? = 14 14 1 2 ) , ( 2 ) , ( pd gcd2 pd vco2 gcd2 pd gcd1 pd vco gcd1 f f and f f gcd f and f f and f f gcd f 1 30 2 10 44 1 10 120 10 44 1 10 2 200 14 3 = > = = gcd f gcd1 30 2 10 44 1 10 20 10 44 1 10 3 200 14 3 = > = = gcd f gcd2 2 if equation 16 is satisfied for at least two of the equally spaced interval (channel) frequencies f vco1 , f vco2 , f vco3 , ... f vcon , as it is in equation 17, hmc832 exact frequency channel mode is possible for all desired channel frequencies, and can be configured as follows: register 0x03 = x2d 0 d 45 10 44 . 61 10 2 . 2800 6 6 = = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? floor f f floor pd vco1 register 0x0c = 0xc00 d 3072 20000 10 44 . 61 ) 10 44 . 61 , 10 100 ( 10 44 . 61 ) ), (( 6 6 3 6 1 = = = = ? + gcd f f f gcd f pd vcok vcok pd were f vcok+1 ? f vcok ) is the desired channel spacing ( 100 khz in this example). 3. to program register 0x04, the closest integer - n boundary frequency, f n , that is less than the smallest channel vco frequency, f vco1 , must be calculated ( f n = floor( f vco1 /f pd )). using the current example: mhz 8 . 2764 10 44 . 61 45 10 44 . 61 10 2 . 2800 6 6 6 = = ? ? ? ? ? ? ? ? = floor f f pd n t en for cannel 1 register 0x04 = ceil ? ? ? ? ? ? ? ? ? pd n vco1 f f f ) ( 2 24 , where f vco1 = 2800.2 mhz. 938000 x 0 d 9666560 10 44 . 61 ) 10 8 . 2764 10 2 . 2800 ( 2 6 6 6 24 = = ? ? ? ? ? ? ? ? ? = ceil 4 to change from channel 1 (f vco1 = 2800.2 mhz) to channel 2 (f vco2 = 2800.3 mhz), only register 0x04 needs to be programmed, as long as all of the desired exact frequencies , f vcok ( figure 46) , fall between the same integer - n boundaries (f n < f vcok < f n + 1 ). in that case, register 0x04 = . on so and , eaab 93 x 0 d 9693867 10 44 . 61 ) 10 8 . 2764 10 3 . 2800 ( 2 6 6 6 24 = = ? ? ? ? ? ? ? ? ? ceil seed register the start phase of the fractio nal modulator digital phase accumulator (dpa) can be set to one of four possible default values via the seed register , register 0x 06[1:0]. the hmc832 automatically reload s the start phase (seed va lue) into the dpa every time a new fractional frequency is selected. certain zero or binary seed values may cause spurious energy correlation at specific frequencies. for most c ases a random (not zero and not binary) start seed is recommended ( register 0x 0 6[1:0] = 2 ). soft reset and power - on reset the hmc832 features a hardware power - on reset (por). all chip registers ar e reset to default states approximately 250 s after power up. the pll subsystem spi registers can also be soft reset by an spi write to register 0x 00. note that the soft reset does not clear the spi mode of operation referred to in the serial port section . n ote that the vco subsystem is not affected by the pll soft reset ; the vco subsystem registers can only be reset by removing the power supply. i f external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( register 0x 00[5] = 1) immediately after power up, before any other spi activity. this write procedure ensure s starting from a known state. rev. a | page 28 of 48
data sheet hmc832 rev. a | page 29 of 48 power-down mode note that the vco subsystem is not affected by the cen or soft reset. therefore, device power-down is a two step process. 1. power down the vco by writing 0 to vco register 1 via register 0x05 . 2. power-down the pll by pulling the cen pin (pin 17) low (assuming there are no spi overrides (register 0x01[0] = 1)). pulling the cen pin low disables all analog functions and internal clocks. current consumption typically drops below 10 a in the power-down state. the serial port still responds to normal communication in power-down mode. it is possible to ignore the cen pin by setting register 0x01[0] = 0. control of the power-down mode then comes from the serial port register, register 0x01[1]. it is also possible to leave various blocks turned on when in power-down (see register 0x01), as listed in table 10. table 10. bit and block assignments for register 0x01 bit assignment block assignment bit 2 internal bias reference sources bit 3 pd block bit 4 cp block bit 5 reference path buffer bit 6 vco path buffer bit 7 digital i/o test pads to mute the output but leave the pll and vco locked, see the vco output mute function section. general-purpose output (gpo) pin the pll shares the ld_sdo (lock detect/serial data output) pin to perform various functions. although the pin is most commonly used to read back registers from the chip via the spi, it is also capable of exporting a variety of signals and real-time test waveforms (including lock detect). it is driven by a tristate cmos driver with ~200 r out . it has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. in its default configuration, after power-on reset, the output driver is disabled, and only drives during appropriately addressed spi reads. this allows it to share the output with other devices on the same bus. the pin driver is enabled if the chip is addressed; that is, the last three bits of spi cycle = 000b before the rising edge of sen. if sen rises before sck has clocked in an invalid (non zero) chip address, the hmc832 starts to drive the bus. to monitor any of the gpo signals, including lock detect, set register 0x0f[7] = 1 to keep the sdo driver always on. this stops the ldo driver from tristating and means that the sdo line cannot be shared with other devices. the hmc832 naturally switches away from the gpo data and exports the sdo during an spi read. to prevent this automatic data selection, and always select the gpo signal, set bit 6 of register 0x0f to 1 to prevent automux of the sdo. the phase noise performance at this output is poor and uncharacterized. also, the gpo output should not be toggling during normal operation because it may degrade the spectral performance. note that there are additional controls available, which may be helpful when sharing the bus with other devices. ? to disable the driver completely, set register 0x08[5] = 0 (it takes precedence over all else). ? to disable either the pull-up or pull-down sections of the driver, register 0x0f[8] = 1 or register 0x0f[9] = 1, respectively. example scenarios are listed in table 11. the signals that are available on the gpo are selected by changing the gpo select register 0x0f[4:0]. table 11. driver scenarios scenario action drive sdo during reads, tristate otherwise (allow bus sharing) none required drive sdo during reads, lock detect otherwise set gpo select register 0x0f[4:0] = 00001b (default) set register 0x0f[7] = 1, prevent gpo driver disable always drive lock detect set register 0x0f[6] = 1, prevent automux of sdo set the gpo select register 0x0f[4:0] = 00001 (default) set register 0x0f[7] = 1, prevent gpo driver disable chip identification pll subsystem version information may be read by reading the content of read only register, chip_id in register 0x00. it is not possible to read the vco subsystem version. serial port the spi protocol has the following general features: ? 3-bit chip address, can address up to eight devices connected to the serial bus. ? wide compatibility with multiple protocols from multiple vendors. ? simultaneous write/read during the spi cycle. ? 5-bit address space. ? 3-wire for write only capability, 4-wire for read/write capability. typical serial port operation can be run with sclk at speeds up to 50 mhz. serial port initialization at power-up at power-up, it is required that both sen and sck lines are initially held low, and that the first rising edge occurs on the sck line before any rising edges occur on the sen line.
hmc832 data sheet if the first rising edge occurs on the sen line before it does on the sck line the hmc832 lp6ge spi interface does not function. in that case , it is necessary to cycle the power to the off and on , and repeat the previous recommended sequence (hold both signals low at power - up and ensure that the first rising edge occurs on the sck line). serial port write operation spi write specifications are listed in the table 2 in the spi write timing characteristics section and a typical write cycle is shown in figure 47. the spi write operation is as follows: 1. the master (host) places 24 - bit data, d23:d0, msb first, on sdi on the first 24 falling edges of sclk. 2. the slave ( hmc8 32 ) shifts in data on sdi on the first 24 rising edges of sclk. 3. the master places a 5 - bit register address to be written to, r4:r0, msb first, on the next five falling edges of sclk (25 th to 29 th falling edges) . 4. the slave shifts the register bits on the next five rising edges of sclk (25 th to 29 th rising edges). 5. the master places 3 - bit chip address, a2:a0, msb first, on the next three falling edges of sclk (30 th to 32 nd falling edges). analog devices reserves chip address a2 to chip address a0 = 000 for a ll rf pll s with integrated vcos. 6. the slave shifts the chip address bits on the next three rising edges of sclk (30 th to 32 nd rising edges). 7. the master asserts sen after the 32 nd rising edge of sclk. 8. the slave registers the sdi data on the rising edge of se n. figure 47 . serial port timing diagram , w rite 1 t 1 t 2 t 5 t 6 t 3 t 4 2 3 22 23 24 25 26 x x d23 d22 d2 d1 d0 a2 a1 a0 r4 r3 r0 30 31 32 sck sdi sen 12827-052 rev. a | page 30 of 48
data sheet hmc832 serial port r ead operation in general, the ld_sdo line is always active during the write cycle. during any spi cycle , ld_sdo contain s the data from the current address written in reg ister 0x 0[4:0]. if reg ister 0x 0[4:0] is not changed , the same data is always present on ld_sdo during a spi cycle . if a read is required from a specific address, it is necessary to write the required address to register 0x0[4:0] in the first spi c ycle, then in the next spi cycle , the desired data becomes available on ld_sdo. a typical read cycle is shown in figure 48. an example of the two cycle procedure to read from any random address is as follows: 1. the m aster (host), on the first 24 falling edges of sclk places 24 - bit data, d 23: d 0, msb f irst, on sdi as shown in figure 48. set d 23: d 5 to zero. d 4: d 0 = address of the register to be read on the next cycle. 2. t he slave ( hmc832 ) shifts in data on sdi on the first 24 rising edges of sck . 3. the m aster places the 5 - bit register address , r 4: r 0, (the read address register), msb first, on the next five falling edges of sck (25 th to 29 th falling edges ). r 4: r 0 = 00000. 4. the s lave shifts the register bits on the next five rising edges of sck (25 th to 29 th rising edges ). 5. the m aster places the 3 - bit chip address, a 2: a 0, msb first, on the next three falling edges of sck (30 th t o 3 2 nd falling edges ). the c hip address is always 000 b. 6. the s lave shifts the chip address bits on the next three rising edges of sck (30 th to 32 nd rising edges ). 7. the master asserts sen after the 32 nd rising edge of sck. 8. the slave registers the sdi data on the rising edge of sen. 9. the master clears sen to complete the the address transfer of the two part read cycle. 10. if a write data to the chip is not needed at the same time as the second cycle occurs , then it is recommended to simply rewrite the same contents on sdi to register 0x00 on the read back p ortion of the cycle. 11. the master places the same sdi data as the previous cycle on the next 32 falling edges of sck. 12. the slave ( hmc832 ) shifts the sdi data on the next 32 rising edges of sck. 13. the s lave places the desired read data ( that is, data from the address specified in register 0x 00[ 4 :0 ] of the first cycle) on ld_sdo , which automatically switches to sdo mode from ld mode, disabling the ld output. 14. the m aster asserts sen after the 32 nd rising edge of sck to complete the cycle and revert back to lock detect on ld_sdo. rev. a | page 31 of 48
hmc832 data sheet figure 48 . serial port timing diagram , r ead 1 t 1 t 5 t 4 t 7 t 6 t 2 18 19 20 read address register address = 00000 first cycle chi p address = 000 24 25 29 30 31 32 r0 r3 d0 d4 d5 x x x ld/gpo sck sdi sen ld_sdo or tris ta te ld/gpo x x x x x x x x x x r4 a2 a1 a0 t 3 1 t 1 t 7 t 6 18 19 20 second cycle 24 25 29 30 31 32 r0 r3 d0 d4 d5 d23 x x d23 ld/gpo sck sdi sen ld_sdo ld/gpo 1 1 f o r mor e i n f o r m a t i o n o n u s i n g t h e g p o p i n w h i l e i n s p i o p e n mo d e p l e a s e s e e s e r i a l p o r t s e c t i o n . d22 d2 d1 d0 r4 r0 a2 a1 a0 r4 a2 a1 a0 t 3 12827-053 rev. a | page 32 of 48
data sheet hmc832 application s information large bandwidth (25 mhz to 3000 mhz), in dustry leading phase noise and spurious performance, excellent noise floor (?160 dbc/hz), coupled with a high level of integration make the hmc832 ideal for a variety of applications; as an rf or if stage local oscillator ( lo ) . using the hmc832 with a tunable reference , as shown in figure 51 , it is possible to drastically improve spurious emissions performance across all frequencies. figure 49 . hmc832 in a typical transmit chain figure 50 . hmc832 in a typical receive chain figure 51 . hmc832 u sed as a tunable reference for hmc832 hmc1044lp3e hmc900lp5e hmc795lp5e hmc832 pll 2 dac dac hmc832 pll 12827-040 hmc597lp4e hmc1044lp3e hmc832 hmc832 hmc900lp5e cmio cmqo hmc960lp4e 90 0 pl l pl l hmcad1520 adc hmcad1520 adc 12827-041 hmc832 c r ys t a l oscill a t or pl l hmc832 tunable reference 25mhz t o 100mhz pl l 12827-042 rev. a | page 33 of 48
hmc832 data sheet power supply the hmc832 is a high performance , low noise device. in some cases , phase noise and spurious performance may be degraded by noisy power supplies. to achieve maximum performance and ensure that power supply noise does not degrade the per - formance of the hmc832 it is recommended to use the analog devices low noise , high power supply rejection ratio ( psrr) regulator, the hmc1060lp3e . using the hmc1060lp3e lowers the design risk and cost, and ensures that the performance shown in the typical performance characteristics section can be achieved. programmable perform ance technology for low power applications that do not require maximum noise floor performance, the hmc832 features the ability to reduce current consumption by 50 ma (power consumption by 165 mw) at the cost of decreasing phase noise floor performance by ~5 db. high performance is enabled by writing vco_reg 0x 03[1:0] = 3d, and it is disabled ( low current consumption mode enabled) by writing vco_reg 0x 03[1:0] = 1d. high performance mode improves noise floor performance at the cost of increased current consumption. resulting current consumption and phase noise floor perfor mance are shown in figure 33 and figure 36. loop filter and frequency change s figure 52 . loop filter design all plls with integrated vcos exhibit integer boundary spurs at harmonics of the reference frequency. as seen in figure 18, the plot shows the worst case spurious scenario where the harmonic of the reference frequency (50 mhz) is within the loop filte r bandwidth of the fundamental frequency of the hmc832 . the tunable reference changes the reference frequency from 50 mhz in figure 18 to 47.5 mhz in figure 16 to distance the harmonic of the reference frequency (spurious emissions) away from the fundamental output frequency of the hmc832 so that it is fil tered by the loop filter. the internal hmc832 setup and divide ratios are changed in the opposite direction accordingly so that the hmc83 2 generates identical output frequency as shown in figure 18 , without the spurious emissions inside the loop bandwidth. using these same procedures, i n figure 19 , the grap h is generated by o bserving and plotting the magnitude of the largest spur only, at any offset, at each output frequency, while using a fixed 50 mhz reference and a tunable 47.5 mhz reference. the hmc832 features an internal a utocalibration process that seamlessly calibrates the hmc832 when a frequency change is executed (see figure 27 and figure 30 ) . typical frequency settling time that can be expected after any frequency change ( writes to reg ister 0x 03 or reg ister 0x 04 ) is shown in figure 27 with a utocalibration e nabled (register 0x 0a[11] = 0). a f re - quency hop of 5 mhz is shown in figure 27 ; however the settling time is independent of the size of the frequency change. any size frequency hop has a similar settling time with a uto calibration enabled. figure 32 shows the typical tuning voltage after calibration where once the hmc832 is c alibrated at any temperature, the calibra tion setting holds across the entire operating range of the hmc832 (?40c to +85c) . figure 32 shows that the tuning voltage is maintained within a narrow operating range for worst case scenarios where calibration was executed at one temperature extreme and the device is operating at the other extreme. for applications that require fast frequency changes, the h mc832 supports manual calibration that enables faster settling times (see figure 28 and figure 31) . manual calibrati on needs to be executed only once for each individual hmc832 , at any tempera - ture, and is valid across all temperature operating range s of the hmc832 . more information about manu al calibration is available in the manual vco calibration for fast frequency hopping section. a frequency hop of 5 mhz is shown in figure 28 and figure 31; however , the settling time is independent of the size of the frequency change. any size frequency hop has a similar settling ti me with a utocalibration disabled (reg ister 0x 0a[11] = 1). table 12 . loop fil ter designs used in typical performance characteristics graphs loop filter type loop filter bw (khz) loop filter phase margin c1 (pf) c2 (nf) c3 (pf) c4 (pf) r2 () r3 () r4 () loop filter design type 1 1 127 61 390 10 82 82 750 300 300 see figure 52 type 2 2 75 61 270 27 200 390 430 390 390 type 3 3 214 71 56 1.8 na na 2200 0 0 1 loop filter type 1 is for best integrated phase noise. loop filter bandwidth is designed for 50 mhz pd frequency, cp = 1.6 ma at 2.2 ghz output in fractional mode. 2 loop filter type 2 is suggested to use for best far out phase noise. loop filter bw is designed for 50 mhz pd frequency, cp = 1.6 ma at 2.2 ghz output in f ractional m ode. 3 loop filter type 3 is suggested to use for best integrated phase noise at integer mode. loop filter b andwidth is designed for 50 mhz pd frequency, cp = 2.5 ma at 3 gh z output in integer mode. cp vtune c4 c3 c1 c2 r2 r3 r4 12827-037 rev. a | page 34 of 48
data sheet hmc832 rf programmable outp ut return loss the hmc832 features programmable rf output return loss (vco_reg 0x 03[5]) and 12 db of programmable gain (vco_reg 0x 07[3:0]) , as shown in figure 26 and figure 25. maximum output power is achieved with a high return loss set ting (vco_reg 0x 03[5] = 0) , as shown in figure 22 . setting vco_reg 0x 03[5] = 1 improves return loss for applications that require i t at the cost of reduced rf output power ( see figure 22 ). mute mode t he hmc832 features a configurable mute mode, along with the ability to independently turn off outputs on both rf_n and rf_p output pins. figure 35 shows isolation measured at the output when the mute mode is on (vco_reg 0x 03[8:7] = 3d), and when the mute mode is off (vco_reg 0x 03[8:7] = 1d) , with either both outputs disabled (vco_reg 0x 03[3:2] = 0) or one output enabled and the other disabled (vco_reg 0x 03 [ 3:2 ] = 1 d). rev. a | page 35 of 48
hmc832 data sheet pll register map id, read address, an d rst registers the id register is read only, the read address/rst strobe register is wri te only, and the rst register is read/write. table 13. register 0 x 00, id register (read only) bit s type name width default description 23:0 r chip_id 24 a 7975 hmc 832 lp 6 ge chip id table 14. register 0x 00, re ad address/rst strobe register (write only) bit s type name width default 1 description 4:0 w read a ddress 5 n/a read a ddress for next cycle , open mode only . this is a write only register. 5 w soft r eset 1 n/a soft r eset for both spi modes (set to 0 for p roper operation) . 23:6 w not d efined 18 n/a not d efined (set to 0 for proper operation) . 1 n/a means not applicable. table 15. register 0x 01, rst register (default 0x000002 ) bit s type name width default description 0 r/w rst_chip en_pin_select 1 0 1 = take pll enable via cen pin, see the power - down mode section 0 = take pll enable via spi (rst_chipen_from_spi) register 0 x 01 [ 1 ] 1 r/w rst_chipen_from_spi 1 1 pll enable bit of the spi 9:2 r/w reserved 8 0 reserved reference divider, i nteger , and fractional frequency registers table 16. register 0x 02, refdiv register (default 0x 000001) bit s type name width default description 13:0 r/w rdiv 14 1 reference d ivide r r v alue (see e quation 12) . using the d ivider requires the analog e n reg ister 0x 08[3] = 1 and d ivider , min imum = 1d , max imum = 16, 383d . table 17. register 0x 03, frequency register , integer part (default 0x 000019) bit s type name w idth default description 18:0 r/w intg_reg 19 25d integer divider register. these bits are the vco divider integer part, used in all modes, see equation 12. fractional m ode . m ax imum 2 19 ? 4 = 0x 7fffc = 524,284d . integer m ode . m in imum 16d . m ax imum 2 19 ? 1 = 0x 7ffff = 524,287d . table 18. register 0x 04, frequency register , fractional part (default 0x 000000) bit s type name width default description 2 3:0 r/w frac 24 0 vco divider fractiona l part (24 - bit unsigned) , see the fractional frequency tuning section. these bits are u sed in fractional mode only (n frac = register 0x 04/2 24 ). m i n imum = 0d ; m ax imum = 2 24 ? 1 . rev. a | page 36 of 48
data sheet hmc832 vco spi register register 0 x 05 is a special register used for indirect addressing of the vco subsystem. writes to register 0 x 05 are automatically forwarded to the vco subsystem by the vco spi state machine controller. register 0x05 is a read/write register. however, register 0x05 holds only the contents of the last transfer to the vco subsystem. therefore, it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. also note special considerations for autocalibration related to register 0 x 05. table 19. register 0x 05, vco spi register (default 0x 000000) bit s type name width default description 2:0 r/w vco_id 3 0 internal vco s ubsystem id . 6:3 r/w vco_regaddr 4 0 vco subsystem register address. these bits are f or interfacing with the vco . s ee the vco serial port interface (vspi) section . 15:7 r/w vco_data 9 0 vco s ubsystem data. these bits are for the d ata to be written to the vco s ubsystem. delta - sigma configuration table 20. register 0x 06, delta - sigma configuration register (default 0x 200b4a) bit type name width default description 1:0 r/w seed 2 2 selects the s eed in f ractional m ode . writes to this register are stored in the hmc832 and are loaded into the modulator only when a frequency change is executed and if register 0x06[8] = 1. 00: 0 seed . 01: lsb seed . 02: 0xb29d08 seed . 03: 0x50f1cd seed . 6:2 r/w reserved 5 18d reserved . 7 r/w frac_bypass 1 0 bypass fractional mode. in the bypass fractional modulator , output is ignored, but fractional modulator continues to be clocked when frac_ rst = 1 . this bit c an be used to test the isolation of the digital fractional modulator from the vco output in integer mode . 0 : use modulator, required for fractional mode 1 : bypass modulator, required for integer mode. 10:8 r/w ini tialization 3 3 d program to 7d . 11 r/w sd enable this bit controls whether autocalibration starts on an integer or a fractional write. 1 1 0: disable s fractional core, use for integer mode or integer mode with csp . 1: enables fractional core, required for fractional mode, or integer isolation testing. 20:12 r/w reserved 9 0 reserved . 21 r/w auto matic clock configuration 1 1 program to 0 . 22 r/w reserved 1 0 reserved . rev. a | page 37 of 48
hmc832 data sheet lock detect register table 21. register 0x 07, l ock detect register (default 0x 00014d) bit type name width default description 2:0 r/w lkd_wincnt_max 3 5 d l ock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect windo w to declare lock 0 : 5 1 : 32 2 : 96 3 : 256 4 : 512 5 : 2048 6 : 8192 7 : 65,535 3 r/w enable internal lock detect 1 1 see the serial port section 5:4 r/w reserved 2 0 reserved 6 r/w lock detect window type 1 1 lock detection window timer selection 1 : digital programmable timer 0 : analog one shot, nominal 10 ns window 9:7 r/w ld digital window duration 3 2 l ock detection, digital window duration 0 : half cycle 1 : one cycle 2 : two cycles 3 : four cycles 4 : eight cycles 5 : 16 cycles 6 : 32 cycles 7 : 64 cycles 11:10 r/w ld digital timer frequency control 2 0 lock detect digital timer frequency control , s ee the lock detect section for more information 00: fastest 11: slowest 12 r/w reserved 31 0 reserved 13 r/w auto matic r elock : one try 1 0 1: a ttempts to relock if lock detect fails for any reason ; t ries on e time only analog enable (en) r egister table 22. register 0x 08, analog en register , (default 0x c1beff) bit type name width default description 4:0 r/w reserved 5 31d reserved 5 r/w gpo_pad_en 1 1 0 : disables the ld / sdo pin 1: enables g po port or allows a shared spi when bit 5 = 1 and register 0xf[7] = 1, the ld_sdo pin is always driven, which is re quired for use of the gpo port when bit 5 = 1 and register 0xf[7] = 0, sdo is off when an unmatched chip address is seen on the spi, allowing a share d spi with other compatible devices 9:6 r/w reserved 4 11d reserved 10 r/w vco buffer and prescaler bias enable 1 1 vco b uffer and prescaler bias enable 20:11 r/w reserved 1 55d reserved rev. a | page 38 of 48
data sheet hmc832 rev. a | page 39 of 48 bit type name width default description 21 r/w high frequency reference 1 0 program to 1 for xtal > 200 mhz 23:22 r/w reserved 2 3d reserved charge pump register table 23. register 0x09, charge pump register (default 0x403264) bit type name width default description 6:0 r/w cp dn gain 7 100d 0x64 charge pump dn gain control, 20 a per step. affects fractional phase noise and lock detect settings. 0d = 0 a 1d = 20 a 2d = 40 a 127d = 2.54 ma 13:7 r/w cp up gain 7 100d 0x64 charge pump up gain control, 20 a per step. affects fractional phase noise and lock detect settings. 0d = 0 a 1d = 20 a 2d = 40 a 127d = 2.54 ma 20:14 r/w offset magnitude 7 0 charge pump offset control, 5 a per step. affects fractional phase noise and lock detect settings. 0d = 0 a 1d = 5 a 2d = 10 a 127d = 635 a 21 r/w offset up enable 1 0 recommended setti ng = 1 in fractional mode, 0 otherwise. 22 r/w offset dn enable 1 1 recommended setting = 0. 23 r/w reserved 1 0 reserved. autocalibration register table 24. register 0x0a, vco autocalibratio n configuration register (default 0x002205) bit type name width default description 2:0 r/w vtune resolution 3 5 r divider cycles 0: 1 cycle 1: 2 cycles 2: 4 cycles 7: 256 cycles 9:3 r/w reserved 7 64d program 8d 10 r/w force curve 1 0 program 0 11 r/w autocalibration disable 1 0 program 0 for normal operation using vco autocalibration 12 r/w no vspi trigger 1 0 0: normal operation 1: this bit disables the serial transfers to the vco subsystem (via register 0x05)
hmc832 data sheet rev. a | page 40 of 48 bit type name width default description 14:13 r/w fsm/vspi clock select 2 1 these bits set the autocalibration fsm and vspi clock (50 mhz maximum) 0: input crystal reference 1: input crystal reference divide by 4 2: input crystal reference divide by 16 3: input crystal reference divide by 32 16:15 r/w reserved 2 0 reserved phase detector (pd) register table 25. register 0x0b, pd register (default 0x0f8061) bit type name width default description 2:0 r/w pd_del_sel 3 1 sets pd reset path delay (recommended setting is 001). 4:3 r/w reserved 2 0 reserved. 5 r/w pd_up_en 1 1 enables the pd up output. 6 r/w pd_dn_en 1 1 enables the pd down output. 8:7 r/w csp mode 2 0 cycle slip prevention mode. this delay va ries by 10% with temperature, and 12% with process. extra current is driven into the loop filter when the phase error is larger than the following: 0 = disabled 1 = 5.4 ns 2 = 14.4 ns 3 = 24.1 ns 9 r/w force cp up 1 0 forces cp up output to turn on; use for test only. 10 r/w force cp dn 1 0 forces cp down output to turn on; use for test only. 23:11 r/w reserved 13 496d 0x1f0 reserved. exact frequency mode register table 26. register 0x0c, exact frequency mode register (default 0x000000) bit type name width default description 13:0 r/w number of channels per f pd 14 0 the comparison frequency divided by the correction rate must be an integer. frequencies at exactly the correction rate have zero frequency error. 0: disabled. 1: disabled. 2:16383d (0x3fff).
data sheet hmc832 general - purpose, serial port interface, and refer ence divider (gpo_sp i_rdiv) register table 27. register 0x 0f , gpo_spi_rdiv register (default 0x 000001) bit type name width default description 4:0 r/w gpo_select 5 1 d the s ignal selected here is an output to the sdo pin when the sdo pin is enable via register 0x08[5] 0: d ata from reg ister 0x 0f[5] 1: lock detect out put 2 : lock detect trigger 3 : lock detect window output 4 : ring oscillator test 5 : pull - up hard from csp 6 : pull - down hard from csp 7 : reserved 8 : reference buffer output 9 : reference divider output 10 : vco divider output 11: modulator clock from vco divider 12: auxiliary clock 13: auxiliary spi clock 14: auxiliary spi enable 15: auxiliary spi data output 16: pd down 17: pd up 18: sd3 clock dela y 19: sd3 core clock 20: autostrobe integer write 21: autostrobe fractional write 22: autostrobe auxiliary spi 23: spi latch enable 24: vco divider sync reset 25: seed load strobe 26 to 29: not used 30: spi output buffer enable 31: soft reset , rst 5 r/w gpo test data 1 0 1 : gpo test data 6 r/w prevent a utomux sdo 1 0 1 : o utputs gpo data only 0 : a utomuxes between sdo and gpo data 7 r/w ldo driver always on 1 0 1 : ld_sdo pin driver always on 0 : ld_sdo pin driver only on during spi read cycle 8 r/w disable pfet 1 0 9 r/w disable nfet 1 0 rev. a | page 41 of 48
hmc832 data sheet vco tune register the vco tune register is a read only register. table 28. register 0x 10, vco tune register (default 0x 000020) bit type name width default description 7:0 r v co switch setting 8 32 indicates the vco switch setting selected by the a utocalibration state machine to yield the nearest free running vco frequency to the desired opera ting frequency. not valid when reg ister 0x 10[8] = 1, a utocalibration b usy. note that when a manual change is made to the vco switch settings , this register does not indicate the current vco switch position. vco subsystems may not use all the msbs, in which case the unused bits are dont care. 0 = highest frequency . 1 = second highest frequency . 255 = lowest frequency . 8 r autocalibration b usy 1 0 busy when the a utocalibration state machine is searching for the nearest switch set ting to the requested frequency. sar register the sar register is a read only register. register 0x 11 , sar register (default 0x 07ffff) bit type name width default description 18:0 r sar error magnitude counts 19 2 19 to 1 sar error magnitude counts 19 r sar error sign 1 0 sar error sign 0 = +ve 1 = ?ve general - purpose 2 register the gpo 2 register is a read only register. table 29. register 0x 12, gpo2 register (default 0x 000000) bit type name width default descripti on 0 r gpo 1 0 gpo s tate 1 r lock d etect 1 0 lock detect status 1 = locked 0 = unlocked built - in self test registe r the bist register is a read only register. table 30. register 0x 13, bist register (default 0x 00125 9) bit type name width default description 16:0 r reserved 17 4697 d reserved rev. a | page 42 of 48
data sheet hmc832 vco subsystem regist er map t he vco subsystem uses indirect addressing via register 0x 05. for more detailed information on how to write to the vco subsystem , see the vco serial port interface (vspi) section . the vco tuning register is write only. table 31. vco_reg 0x 00 tuning bit type name width default description 0 w c al 1 0 vco tune voltage is redirected to a te mperature compensated calibration voltage 8:1 w caps 8 16 vco sub band selection 0 : maximum frequency 1111 1111: minimum frequency vco enable register the vco enable register is a write only register. table 32. vco_re g 0x 01 enable bit type name width default description 0 w master e nable vco s ubsystem 1 1 0 : a ll vco subsystem blocks are turned o ff. 1 w vco e nable 1 1 enables vcos . 2 w pll buffer enable 1 1 enables pll b uffer to n d ivider . 3 w i nput/output master en able 1 1 enables output stage and the output divider . it does not enable/disable the vco. 4 w reserved 1 1 reserved . 5 w output stage enable 1 1 output stage enabl e . 7:6 w reserved 2 3 reserved . 8 w reserved 1 1 reserved . example: disabling the outp ut s tage of the vco subsystem to disable the output stage of the vco subsystem of the hmc832 , clear bit 5 in vco_reg 0x01. if the other bits are left unchanged, then write 1 1101 1111 into vco_reg 0 x 01. the vco subsystem register is accessed via a write to pll subsystem register 0 x 05 = 1 1101 1111 0001 00 = 0 xef 88. register 0 x 05[ 2:0 ] = 000 ; vco subsystem id 0 . register 0 x 05[ 6:3 ] = 0001 ; vco subsystem register address. register 0x05[7] = 1; master e nable. register 0 x 05[ 8 ] = 1 ; vco enable. register 0 x 05[ 9 ] = 1 ; pll buffer enable. register 0 x 05[ 10 ] = 1 ; i/o master enable. register 0 x 05[ 11 ] = 1 ; reserved. register 0 x 05[ 12 ] = 0 ; disable the output stage. register 0 x 05[ 14:13 ] = 11b. register 0x05[15] = 1; dont care. rev. a | page 43 of 48
hmc832 data sheet vco output divider r egister this is a write only register. note that to write 0_1111_1110 into vco_reg 0x02 vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to register 0x05 = 0 _ 1111_ 1110, 0010, 000 b. register 0 x 05[ 2:0 ] = 000 ; subsystem id 0 register 0 x 05[ 6:3 ] = 0010 ; vco register address 2 d. register 0 x 05[ 16:7 ] = 0 _ 1111 _ 1110 ; divide by 62 , maximum output rf gain. table 33. vco_reg 0x 02 vco output divi der bit type name width default description 5:0 w rf d ivide ratio 6 1 0 : mutes the output when vco_reg 0x 03 [ 8:7 ] = 0 d 1: fo 2 : fo/ 2 3 : invalid, defaults to 2 4 : fo/ 4 5 : invalid, defaults to 4 6 : fo/ 6 60 : fo/ 60 61 : invalid, defaults to 60 62 : fo/ 62 > 62 invalid, defaults to 62 8:6 w reserved 3 0 reserved vco configuration re gister the vco configuration register is a write only register. table 34. vco_reg 0x 03 config uration bit type name width default description 1:0 w programmable performance mode 2 2 selects output noise floor performance level at a cost of increased current consumption . 01 : low current consumption mode. 11: high performance mode . other states ( 00 and 10 ) not supported. 2 w rf_n output enable 1 0 enables the output on rf_n pin. required for differential operation, or single - ended output on the rf_n pin. 3 w rf_p output enable 1 0 enables the output on rf_p pin. required f or differential operation, or single - ended output on the rf_p pin. 4 w reserved 1 1 reserved . 5 w return l oss 1 0 0: return loss = ? 5 db t ypical ( h ighest output power) . 1 : return loss = ? 10 db typical. 6 w reserved 1 0 reserved . 8:7 w mute m ode 2 1 defines when the mute function is enabled (the output is muted), see the vco output mute function section , and figure 35 for more information . 00: enables mute when the divide ratio , vco_reg 0x02[5:0] = 0. this enables the hmc832 to be backwards compatible to the hmc830 mute function. 01: during vco calibration (s ee the vco calibration section for more details). 10: n ot supp orted . 11: m ute all rf outputs (unconditional) . rev. a | page 44 of 48
data sheet hmc832 vco calibration/bias , cf calibration, an d msb calibration re gisters these registers are write only. note that, specified performance is only guaranteed with the required settings in table 35 only; other settings are not supported. table 35. vco_reg 0x 04 cal /bias bit type name width default description 0 w initialization 9 201 d reserved table 36. vco_reg 0x 05 cf _ cal bit type name width default description 8:0 w reserved 9 170 d reserved table 37. vco_reg 0x 06 msb cal ibration bit type name width default description 8:0 w reserved 9 255 d reserved vco output power con trol the vco power co ntrol register is write only. table 38. vco_reg 0x 07 output power control bit type name width default description 3:0 w output stage gain control 4 1 output stage gain control in 1 db steps 0d: 0 db gain 1d: 1 db gain 2d: 2 db gain 10d: 10 db gain 11d: 11 db gain 4 w initialization 1 0 program to 1 d 8:5 w reserved 4 4 d program 4 d rev. a | page 45 of 48
hmc832 data sheet rev. a | page 46 of 48 evaluation printed circuit board (pcb) figure 53. silk screen and pcb traces top layer figure 54. silk screen and pcb traces bottom layer the circuit board used in the application uses rf circuit design techniques. signal lines have 50 impedance whereas the package ground leads and exposed paddle are connected directly to the ground plane similar to that shown in figure 53 and figure 54. use a sufficient number of via holes to connect the top and bottom ground planes. the evaluation circuit board shown figure 53 and figure 54 is available from analog devices upon request. changing evaluation board reference frequency and cp current configuration the evaluation board is provided with a 50 mhz on board reference oscillator, and type 1 loop filter configuration, as shown in figure 52 (~127 khz bandwidth, see table 12). the default register configuration file included in the analog devices pll evaluation software sets the comparison frequency to 50 mhz (r = 1, that is, register 0x02 = 1). as with all plls and pll with integrated vcos, modifying the comparison frequency or charge pump (cp) current results in changes to the loop dynamics and ultimately, phase noise performance. when making these changes there are several items to keep in mind: ? cp offset current setting: refer to the charge pump (cp) and phase detector (pd) section. ? ld configuration: refer to the lock detect section. to redesign the loop filter for a particular application, download the pll design software tool by clicking on the software download link on the hmc832 product page. analog devices pll design enables users to accurately model and analyze performance of all analog devices plls, plls with integrated vcos, and clock generators. it supports various loop filter topologies, and enables users to design custom loop filters and accurately simulate resulting performance. for more information, see the loop filter and frequency changes section. for evaluation purposes, the hmc832 evaluation board is shipped with an on-board, low cost, low noise (100 ppm), 50 mhz vcxo, enabling evaluation of most parameters including phase noise without any external references. exact phase or frequency measurements require the hmc832 to use the same reference as the measuring instrument. to accommodate this requirement, the hmc832 evaluation board includes the hmc1031ms8e ; a simple low current integer-n pll that can lock the on-board vcxo to an external 10 mhz reference input commonly provided by most test equipment. to lock the hmc832 to an external 10 mhz reference, connect the external reference output to the j5 input of the hmc832 evaluation board and change the hmc1031ms8e integer divider value to 5 by changing the switch settings, d1 = 1 (sw1 to sw4 closed), and d0 = 0 (sw2 to sw3 open), for more information see the hmc1031ms8e data sheet. evaluation kit contents the evaluation kit contains one hmc832 lp6ge evaluation pcb, a usb interface board, a six-foot usb a-male to usb b-female cable, a cd rom that contains the user manual, evaluation pcb schematic, evaluation software, and analog devices pll design software. to order the evaluation kit, see the ordering guide section for the product number. 12827-039 12827-139
data sheet hmc832 outline dimensions figure 55 . 40 - lead quad flat no - lead package [qfn] 6 mm 6 mm body, very thin quad dimensions shown in inches and [millimeters] figure 56 . tape and reel outline dimensions dimensions shown in millimeters 1 1-10-2014- a n ot es : 1 . p a c k a g e b o d y m a t e r i a l : l o w st r e s s i n j ec t i o n mo l d e d p l a st i c si l i ca a n d si l i c o n i m p r e g n a t e d . 2 . l e a d a n d g r ou n d p a d d l e m a t e r i a l : co pp e r a l l o y . 3 . l e a d a n d g r ou n d p a d d l e p l a t i n g: 1 0 0 % m a t t e t i n . 4 . d i m e n s i o n s a r e i n i n ch e s [ m i l l i m e t e r s ] . 5 . l e a d s p a ci n g t o l e r a n c e i s no n - c um u l a t i v e . 6 . p a d b u r r l e n g t h s ha l l b e 0 . 1 5 m m m a x . p a d b u r r h e i gh t s ha l l b e 0. 2 5 m m max. 7 . p a c k a g e w a r p s ha l l n ot e x c e e d 0. 0 5 m m. 9 . r e f e r to h i t ti t e a p p l i ca t i o n n ot e f o r sugg e st e d p c b l a n d p a t t e r n . for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 1 1-03-2014- a rev. a | page 47 of 48
hmc832 data sheet ordering guide model 1 lead finish ms l rating temperature package description qty. brand 2 hmc 832 lp 6 ge 100% matte sn msl 1 ?40c to + 85 c 40 - lead quad flat no - lead package [qfn], low stress injection molded plastic xxxx 832h hmc 832 lp 6 getr 100% matte sn msl 1 40 c to + 85 c 40 - lea d quad flat no - lead package [qfn], low stress injection molded plastic, 7 ? tape and reel 500 xxxx 832h ekit 01 - hmc 832lp 6g e valuation kit eval 01- hmc 832 lp 6g e valuation board 1 e = rohs compliant part. 2 four - digit l ot n umber x xxx. ? 2014 an alog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12827 -0- 11/14(a) rev. a | page 48 of 48

▲Up To Search▲

Price & Availability of EKIT01-HMC832LP6G

	To Download EKIT01-HMC832LP6G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .